Homomorphic operation accelerator and homomorphic operation performing device including the same

Patent metadata

Field	Value
Publication number	US-11539504-B2
Application number	US-202117336625-A
Country	US
Kind code	B2
Filing date	Jun 2, 2021
Priority date	Oct 12, 2020
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

A homomorphic operation accelerator includes a plurality of circuits and a homomorphic operation managing circuit. The plurality of circuits may perform homomorphic operations. The homomorphic operation managing circuit may receive cipher text data, homomorphic encryption information and homomorphic operation information from an external device. The homomorphic operation managing circuit may activate or deactivate each of a plurality of enable signals applied to the plurality of circuits based on the homomorphic encryption information and the homomorphic operation information. The homomorphic operation managing circuit may activate or deactivate each of the plurality of circuits based on the plurality of enable signals. The homomorphic encryption information may be associated with a homomorphic encryption algorithm used to generate the cipher text data. The homomorphic operation information may be associated with the homomorphic operations to be performed on the cipher text data.

First claim

What is claimed is:

1. A homomorphic operation accelerator comprising:
a plurality of circuits configured to perform homomorphic operations; and
a homomorphic operation managing circuit configured to:
receive ciphertext data, homomorphic encryption information and homomorphic operation information, the homomorphic encryption information being associated with a homomorphic encryption algorithm used to generate the ciphertext data, and the homomorphic operation information being associated with homomorphic operations to be performed on the ciphertext data;
selectively activate or deactivate each of a plurality of enable signals applied to the plurality of circuits based on the homomorphic encryption information and the homomorphic operation information; and
activate or deactivate each of the plurality of circuits based on the plurality of enable signals,
wherein the homomorphic operations are performed on the ciphertext data based on activated circuits among the plurality of circuits,
wherein, based on the homomorphic operations corresponding to a first arithmetic operation and the homomorphic encryption algorithm being a first type of homomorphic encryption algorithm, the homomorphic operation managing circuit is further configured to deactivate a first type of circuit, among the plurality of circuits, and
wherein, based on the homomorphic operations corresponding to a second arithmetic operation and the homomorphic encryption algorithm being a second type of homomorphic encryption algorithm, the homomorphic operation managing circuit is further configured to deactivate a second type of circuit, among the plurality of circuits.

2. The homomorphic operation accelerator of claim 1 , wherein:
the plurality of circuits include a homomorphic multiplier including a Chinese remainder theorem (CRT) circuit, an inverse CRT circuit, a number theoretic transform (NTT) circuit, an inverse NTT circuit, a modular shift up circuit, a modular shift down circuit, a modular adder and a modular multiplier, and
based on the homomorphic operations corresponding to a homomorphic addition, the homomorphic operation managing circuit is further configured to deactivate the CRT circuit, the inverse CRT circuit, the NTT circuit, the inverse NTT circuit, the modular shift up circuit, the modular shift down circuit, the modular adder and the modular multiplier.

3. The homomorphic operation accelerator of claim 1 , wherein:
the plurality of circuits include a homomorphic multiplier including a Chinese remainder theorem (CRT) circuit, an inverse CRT circuit, a number theoretic transform (NTT) circuit, an inverse NTT circuit, a modular shift up circuit, a modular shift down circuit, a modular adder and a modular multiplier, and
based on the homomorphic operations corresponding to a homomorphic multiplication and the homomorphic encryption algorithm is based on a residual number system (RNS), the homomorphic operation managing circuit is further configured to deactivate the CRT circuit and the inverse CRT circuit and configured to activate the NTT circuit, the inverse NTT circuit, the modular shift up circuit, the modular shift down circuit, the modular adder and the modular multiplier.

4. The homomorphic operation accelerator of claim 1 , wherein:
the plurality of circuits include a homomorphic multiplier including a Chinese remainder theorem (CRT) circuit, an inverse CRT circuit, a number theoretic transform (NTT) circuit, an inverse NTT circuit, a modular shift up circuit, a modular shift down circuit, a modular adder and a modular multiplier, and
based on the homomorphic operations corresponding to a homomorphic multiplication and the homomorphic encryption algorithm is based on a number system other than a RNS, the homomorphic operation managing circuit is further configured to activate the CRT circuit, the inverse CRT circuit, the NTT circuit, the inverse NTT circuit, the modular shift up circuit, the modular shift down circuit, the modular adder and the modular multiplier.

5. The homomorphic operation accelerator of claim 1 , wherein:
the plurality of circuits include a first key switching circuit corresponding to a first homomorphic encryption algorithm, a second key switching circuit corresponding to a second homomorphic encryption algorithm, a third key switching circuit corresponding to a third homomorphic encryption algorithm, and a fourth key switching circuit corresponding to a fourth homomorphic encryption algorithm, and
based on the homomorphic encryption algorithm corresponding to the first homomorphic encryption algorithm, the homomorphic operation managing circuit is further configured to activate the first key switching circuit and is further configured to deactivate the second key switching circuit, the third key switching circuit and the fourth key switching circuit.

6. The homomorphic operation accelerator of claim 1 , wherein:
the plurality of circuits include a homomorphic adder, a homomorphic multiplier and a bootstrapping circuit; and
the homomorphic operation managing circuit is further configured to control one of the homomorphic adder, the homomorphic multiplier and the bootstrapping circuit based on the homomorphic encryption information and the homomorphic operation information to perform one of a homomorphic addition, a homomorphic multiplication and a bootstrapping on the cipher text data.

7. The homomorphic operation accelerator of claim 6 , wherein:
based on the homomorphic operations corresponding to a homomorphic addition, the homomorphic operation managing circuit is further configured to activate the homomorphic adder, and deactivate the homomorphic multiplier and the bootstrapping circuit.

8. The homomorphic operation accelerator of claim 6 , wherein:
based on the homomorphic operations corresponding to a homomorphic multiplication, the homomorphic operation managing circuit is further configured to activate the homomorphic multiplier and deactivate the homomorphic adder and the bootstrapping circuit.

9. The homomorphic operation accelerator of claim 1 , wherein:
the homomorphic encryption algorithm includes a first homomorphic encryption algorithm, a second homomorphic encryption algorithm, a third homomorphic encryption algorithm and a fourth homomorphic encryption algorithm, each of the first to fourth homomorphic encryption algorithms being a grid-based encryption algorithm,
the first and the third homomorphic encryption algorithms are based on an integer number system,
the second and the fourth homomorphic encryption algorithms are based on a complex number system,
the first and the second homomorphic encryption algorithms are based on a number system other than a residual number system (RNS), and
the third and the fourth homomorphic encryption algorithms are based on the RNS.

10. The homomorphic operation accelerator of claim 1 , wherein:
the homomorphic operations include a homomorphic addition and a homomorphic multiplication, and
the homomorphic operation information includes logical or temporal information for sequentially performing the homomorphic addition or the homomorphic multiplication.

11. The homomorphic operation accelerator of claim 1 , wherein:
the plurality of circuits include a homomorphic multiplier, which comprise a plurality of Chinese remainder theorem-number theoretic transform CRT-NTT circuits and a plurality of inverse NTT-inverse CRT (INTT-ICRT) circuits, and
the homomorphic operation managing circuit is further configured to activate or deactivate each of the plurality of CRT-NTT circuits and the plurality of INTT-ICRT circuits based on the homomorphic encryption information and the homomorphic operation information.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Na Hanbyeul
• Kim Sumin
• Son Hongrak
• Shin Junho

Classifications

• H04L9/3093

  involving Lattices or polynomial equations, e.g. NTRU scheme · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title

• H04L9/008 Primary

  involving homomorphic encryption · CPC title

• H04L2209/125

  Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations · CPC title

• H04L9/3006

  underlying computational problems or public-key parameters · CPC title