Semiconductor integrated circuit and reception device

Patent metadata

Field	Value
Publication number	US-11539390-B2
Application number	US-202017016965-A
Country	US
Kind code	B2
Filing date	Sep 10, 2020
Priority date	Sep 18, 2019
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

According to one embodiment, in a semiconductor integrated circuit, a sampler is connected to an output node of a summer circuit. A shift register is connected to an output node of the sampler and includes K stages of registers, K being an integer that is equal to or larger than 3. To a control circuit, output nodes of respective registers of N-th to M-th stages among the K stages of registers are connected, N being an integer larger than 1 and smaller than K, M being an integer larger than N and equal to or smaller than K. A first switch includes one end connected to the output node of the summer circuit. A correction circuit includes a first control node that is connected to the control circuit through a first feedback line and an output node to which a second end of the first switch is connected.

First claim

What is claimed is:

1. A semiconductor integrated circuit comprising:
a summer circuit;
a sampler electrically connected to an output node of the summer circuit;
a shift register that is electrically connected to an output node of the sampler and includes K stages of registers, K being an integer that is equal to or larger than 3;
a control circuit to which output nodes of respective registers of N-th to M-th stages among the K stages of registers are electrically connected, N being an integer larger than 1 and smaller than K, M being an integer larger than N and equal to or smaller than K;
a first switch including one end electrically connected to the output node of the summer circuit; and
a correction circuit including a first control node that is electrically connected to the control circuit through a first feedback line and an output node to which a second end of the first switch is electrically connected.

2. The semiconductor integrated circuit according to claim 1 , wherein the correction circuit further includes a second control node that is electrically connected to the control circuit through a second feedback line.

3. The semiconductor integrated circuit according to claim 2 , wherein
the control circuit is configured to supply a first control signal corresponding to a first tap coefficient in a plurality of tap coefficients to the first feedback line when data output from the registers of the N-th to the M-th stages matches a first pattern, and to supply a second control signal corresponding to a second tap coefficient in the plurality of tap coefficients to the second feedback line when the data output from the registers of the N-th to the M-th stages matches a second pattern,
the correction circuit is configured to generate a correction signal using the first tap coefficient when the first control node receives the first control signal through the first feedback line, and to generate a correction signal using the second tap coefficient when the second control node receives the second control signal through the second feedback line, and
the generated correction signal is transmitted to output node of the summer circuit when the first switch is turned ON.

4. The semiconductor integrated circuit according to claim 2 , wherein
the control circuit is configured to supply a first control signal corresponding to a first tap coefficient in a plurality of tap coefficients to the first feedback line when an appearance probability of a given bit value in data output from the registers of N-th to M-th stages is included in a first range, and to supply a second control signal corresponding to a second tap coefficient in the plurality of tap coefficients to the second feedback line when the appearance probability of the given bit value in the data output from the registers of the N-th to M-th stages is included in a second range,
the correction circuit is configured to generate a correction signal using the first tap coefficient when the first control node receives the first control signal through the first feedback line, and to generate a correction signal using the second tap coefficient when the second control node receives the second control signal through the second feedback line, and
the generated correction signal is transmitted to the output node of the summer circuit when the first switch is turned ON.

5. The semiconductor integrated circuit according to claim 2 , wherein the correction circuit further includes:
a first current source;
a second switch including a third end electrically connected to the first current source and a fourth end electrically connected to the output node thereof, and configured to be turned ON or OFF based on a control signal received by the first control node;
a second current source; and
a third switch including a fifth end electrically connected to the second current source and a sixth end electrically connected to the output node thereof, and configured to be turned ON or OFF based on a control signal received by the second control node.

6. The semiconductor integrated circuit according to claim 2 , wherein the correction circuit further includes:
a first variable current source;
a second switch including a third end electrically connected to the first variable current source and a fourth end electrically connected to the output node thereof, and configured to be turned ON or OFF based on a control signal received by the first control node;
a second variable current source; and
a third switch including a fifth end electrically connected to the second variable current source and a sixth end electrically connected to the output node thereof, and configured to be turned ON or OFF based on a control signal received by the second control node.

7. The semiconductor integrated circuit according to claim 2 , wherein the control circuit includes:
a first comparator circuit configured to compare a pattern of data output from the registers of the N-th to the M-th stages with a first pattern, and to supply a first control signal corresponding to a result of the comparison to the first feedback line; and
a second comparator circuit configured to compare the pattern of the output data with a second pattern, and to supply a second control signal corresponding to a result of the comparison to the second feedback line.

8. The semiconductor integrated circuit according to claim 2 , wherein the control circuit includes:
a first comparator circuit configured to compare an appearance probability of a given bit value in data output from the registers of the N-th to the M-th stages with a first range, and to supply a first control signal corresponding to a result of the comparison to the first feedback line; and
a second comparator circuit configured to compare the appearance probability of the given bit value in the output data with a second range, and to supply a second control signal corresponding to a result of the comparison to the second feedback line.

9. The semiconductor integrated circuit according to claim 2 , wherein
the correction circuit is electrically connected to the control circuit through a first coefficient control line and a second coefficient control line, and
the control circuit includes:
a first comparator circuit configured to compare a pattern of data output from the registers of the N-th to the M-th stages with a first pattern, and to supply a first control signal corresponding to a result of the comparison to the first feedback line;
a second comparator circuit configured to compare the pattern of the output data with a second pattern, and to supply a second control signal corresponding to a result of the comparison to the second feedback line;
a first calculation circuit configured to calculate a first tap coefficient corresponding to the first pattern based on the pattern of the output data, and to supply a first coefficient control signal based on a result of the calculation to the first coefficient control line; and
a second calculation circuit configured to calculate a second tap coefficient corresponding to the second pattern based on the pattern of the output data, and to supply a second coefficient control signal based on a result of the calculation to the second coefficient control line.

10. The semiconductor integrated circuit according to claim 2 , wherein
the correction circuit is electrically connected to the control circuit through a first coefficient control line and a second coefficient control line, and
the control circuit includes:
a first comparator circuit configured to compare an appearance probability of a given bit value in data output from the registers of the N-th to the M-th stages with a first range, and to s

Assignees

• Kioxia Corp

Inventors

• Iwai Takayuki

Classifications

• H04L25/0272

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• H04L25/03878 Primary

  Line equalisers; line build-out devices · CPC title

• H04L25/0292

  Arrangements specific to the receiver end · CPC title

• H04L25/03057

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04B1/24 Primary

  the receiver comprising at least one semiconductor device having three or more electrodes · CPC title