Chip component manufacturing method

Patent metadata

Field	Value
Publication number	US-11538983-B2
Application number	US-202016812742-A
Country	US
Kind code	B2
Filing date	Mar 9, 2020
Priority date	Sep 12, 2017
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

Provided is a chip component manufacturing method which enables a plurality of chip pieces to be handled while being pasted to a sheet, and in which it is possible to apply at least a surface treatment to a plurality of chip pieces while being pasted to a sheet. This chip component manufacturing method comprises: a step for retaining a green sheet or the like on a carrier sheet; a step for cutting, together with a portion of the carrier sheet, the green sheet or the like retained on the carrier sheet; a step for removing, together with a portion of the carrier sheet, at least a dummy portion of the green sheet or the like that has been cut, so as to leave a plurality of chip pieces on the carrier sheet; and a step for applying at least a surface treatment to lateral surface portions of the plurality of chip pieces that have become exposed due to the removing while the plurality of chip pieces are being retained on the carrier sheet.

First claim

The invention claimed is:

1. A chip component manufacturing method, comprising the steps of:
holding a ceramic green sheet or green laminate on a first carrier sheet;
cutting the green sheet or green laminate held on the first carrier sheet together with part of the first carrier sheet;
removing part of the green sheet or green laminate, after having been cut, that is not used as at least a product, together with part of the first carrier sheet, and leaving a plurality of chip pieces on the first carrier sheet; and
with the plurality of chip pieces being held on the first carrier sheet, applying at least a surface treatment to side surface portions of the plurality of chip pieces that have been exposed by removing the part of the green sheet or green laminate that is not used as at least the product;
wherein the surface treatment includes applying a paste to form at least one electrode film.

2. The chip component manufacturing method according to claim 1 , further comprising the steps of:
holding the plurality of chip pieces on a second carrier sheet and then removing the plurality of chip pieces from the first carrier sheet on which the plurality of chip pieces were held originally;
cutting the chip pieces held on the second carrier sheet together with part of the second carrier sheet;
removing parts of the chip pieces, after having been cut, that are not used as at least products, together with part of the second carrier sheet, and leaving a plurality of chip pieces on the second carrier sheet; and
with the plurality of chip pieces being held on the second carrier sheet, applying at least a surface treatment to other side surface portions of the plurality of chip pieces that have been exposed by removing the parts of the chip pieces that are not used as at least products.

3. The chip component manufacturing method according to claim 1 , wherein the first carrier sheet has a laminated structure including two or more sheets, each sheet including a base layer and an adhesive layer formed on one surface of the base layer.

4. The chip component manufacturing method according to claim 3 , wherein the adhesive layer of at least one of the two or more sheets of the laminated structure of the first carrier sheet has an adhesive strength that decreases with exposure to a change in temperature or exposure to ultraviolet irradiation.

5. The chip component manufacturing method according to claim 3 , wherein each of the adhesive layers of the two or more sheets of the laminated structure has an adhesive strength that is set arbitrarily, and the adhesive strength of each of the adhesive layers of the two or more sheets of the laminated structure of the first carrier sheet is the same or different.

6. The chip component manufacturing method according to claim 3 , wherein
the first carrier sheet includes a laminate of a first sheet and a second sheet,
the first sheet includes a first base layer and a first adhesive layer on which the green sheet or green laminate is held, and
the second sheet includes a second base layer and a second adhesive layer on which the first sheet is held.

7. The chip component manufacturing method according to claim 6 , wherein the first adhesive layer has a lower adhesive strength than the second adhesive layer.

8. The chip component manufacturing method according to claim 7 , wherein the second adhesive layer has an adhesive strength that is equal to or greater than four times the adhesive strength of the first adhesive layer.

9. The chip component manufacturing method according to claim 6 , wherein the first adhesive layer has a thickness which is smaller than that of the second adhesive layer.

10. The chip component manufacturing method according to claim 6 , wherein the first adhesive layer has an adhesive strength equal to or greater than 0.05 N/25 mm and a thickness equal to or less than 10 μm.

11. The chip component manufacturing method according to claim 6 , wherein the second adhesive layer has an adhesive strength equal to or greater than 0.4 N/25 mm and a thickness equal to or less than 40 μm.

Assignees

• Ngk Insulators Ltd
• Ngk Ceram Device Co Ltd

Inventors

• Oguma Isamu
• Ogata Takatomo
• Funabashi Shigeru
• Ota Hidetake

Classifications

• H10P72/7402

  Wafer tapes, e.g. grinding or dicing support tapes · CPC title

• H10P72/7404

  the wafer tape being a laminate of three or more layers, e.g. including additional layers beyond a base layer and an uppermost adhesive layer · CPC title

• H01G4/30

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H10P72/7416

  used during dicing or grinding · CPC title

• H10P72/70

  for supporting or gripping · CPC title