Bidirectional blocking monolithic heterogeneous integrated cascode-structure field effect transistor, and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11538930-B2
Application number	US-202117201234-A
Country	US
Kind code	B2
Filing date	Mar 15, 2021
Priority date	Jul 30, 2020
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

A bidirectional blocking monolithic heterogeneous integrated Cascode-structure field effect transistor, which mainly solves a problem that the existing monolithic heterogeneous integrated Cascode-structure field effect transistor has no reverse blocking characteristic. The field effect transistor includes a substrate, a GaN buffer layer, an AlGaN barrier layer and a SiN isolation layer, wherein an isolation groove is etched in the middle of the SiN isolation layer, a Si active layer is printed on the SiN isolation layer on one side of the isolation groove so as to prepare a Si metal oxide semiconductor field effect transistor, and a GaN high-electron-mobility transistor is prepared on the other side of the isolation groove, and a drain electrode of the GaN high-electron-mobility transistor is in Schottky contact with the AlGaN barrier layer to form a bidirectional blocking monolithic heterogeneous integrated Cascode-structure field effect transistor.

First claim

What is claimed is:

1. A bidirectional blocking monolithic heterogeneous integrated Cascode-structure field effect transistor, which comprises:
from bottom to top:
a substrate ( 1 ),
a GaN buffer layer ( 2 );
an AlGaN barrier layer ( 3 );
a SiN isolation layer ( 4 ) having in the middle thereof an isolation groove ( 15 ) etched to the GaN buffer layer ( 2 );
a Si active layer ( 5 ) arranged on the SiN isolation layer ( 4 ) on one side of the isolation groove ( 15 );
a first source electrode ( 9 ) and a first drain electrode ( 12 ) arranged on both sides of the Si active layer ( 5 );
a gate dielectric layer ( 10 ) arranged between the first source electrode and the first drain electrode;
a first gate electrode ( 11 ) arranged on the gate dielectric layer ( 10 ) to form a Si metal oxide semiconductor field effect transistor; and
a second source electrode ( 6 ), a second gate electrode ( 7 ) and a second drain electrode ( 8 ) transversely and sequentially arranged on the AlGaN barrier layer ( 3 ) on the other side of the isolation groove ( 15 ) to form a GaN high-electron-mobility transistor,
wherein the second drain electrode ( 8 ) forms Schottky contact with the AlGaN barrier layer ( 3 ) to block the reverse conduction of the GaN high-electron-mobility transistor and realize a reverse blocking characteristic of the Cascode-structure field effect transistor.

2. The transistor of claim 1 , wherein the Si active layer ( 5 ) is printed on the SiN isolation layer ( 4 ) on one side of the isolation groove to form a heterogeneous integrated monolithic chip of Si and GaN.

3. The transistor of claim 1 , wherein:
the first drain electrode ( 12 ) and the second source electrode ( 6 ) are electrically connected through a first metal interconnection strip ( 13 ), and
the first source electrode ( 9 ) and the second gate electrode ( 7 ) are electrically connected through a second metal interconnection strip ( 14 ).

4. The transistor of claim 1 , wherein:
the first gate electrode ( 11 ) is made of tantalum nitride, and
the first source electrode ( 9 ) and the first drain electrode ( 12 ) are both made of nickel, and respectively form ohmic contact with the Si active layer ( 5 ).

5. The transistor of claim 1 , wherein:
the second gate electrode ( 7 ) and the second drain electrode ( 8 ) are both made of nickel and gold, and the second gate electrode ( 7 ) forms Schottky contact with the AlGaN buffer layer ( 3 ), and
the second source electrode ( 6 ) is made of titanium, aluminum, nickel and gold from bottom to top, and forms ohmic contact with the AlGaN buffer layer ( 3 ).

6. The transistor of claim 1 , wherein:
the second source electrode ( 6 ) has a thickness of 262 nm, and
the second gate electrode ( 2 ) and the second drain electrode ( 3 ) both have a thickness of 150-270 nm.

7. The transistor of claim 1 , wherein:
the substrate ( 1 ) has a material of sapphire, silicon carbide or silicon, and a thickness of 400-500 μm,
the GaN buffer layer ( 2 ) has a thickness of 1-2 μm,
the AlGaN barrier layer ( 3 ) has a thickness of 20-30 nm,
the SiN isolation layer ( 4 ) has a thickness of 150-200 nm, and
the first metal interconnection strip ( 13 ) and the second metal interconnection strip ( 14 ) both have a thickness of 200-300 nm.

8. The transistor of claim 1 , wherein:
the Si active layer ( 5 ) has a thickness of 100-200 nm,
the first gate electrode ( 11 ) has a thickness of 100-200 nm,
the first source electrode ( 9 ) and the first drain electrode ( 12 ) both have a thickness of 30-100 nm, and
the gate dielectric layer ( 10 ) between the first source electrode ( 9 ) and the first drain electrode ( 12 ) has a thickness of 20-30 nm.

9. A method for manufacturing a bidirectional blocking monolithic heterogeneous integrated Cascode-structure field effect transistor, the method comprising:
employing metal organic chemical vapor deposition and atomic layer deposition processes to epitaxially grow a GaN buffer layer on a substrate; to epitaxially grow a AlGaN barrier layer on the GaN buffer layer; to deposit a SiN isolation layer on the AlGaN barrier layer, so as to obtain a SiN/AlGaN/GaN/substrate chip;
employing photolithography and reactive ion etching processes to form a monocrystalline silicon thin-film island on a SOI wafer;
employing a wet etching process to etch away a buried oxide layer not covered by the monocrystalline silicon thin-film island from the monocrystalline silicon thin-film island on the SOI wafer in a 49% HF solution;
employing a photolithography process to make anchor points at an edge of the monocrystalline silicon thin-film, so as to prevent the monocrystalline silicon thin-film from shifting and falling off after subsequently the buried oxide layer is etched away completely;
employing a wet etching process to completely etch away the buried oxide layer from the sample provided with the anchor points in a 49% HF solution, so that the monocrystalline silicon thin-film falls onto the base of the SOI wafer;
employing a transfer printing technology to transfer the monocrystalline silicon thin-film, that fell onto the base of the SOI wafer, onto the SiN/AlGaN/GaN/substrate chip;
employing photolithography and reactive ion etching processes to etch an isolation groove with a depth of 300-350 nm on the SiN/AlGaN/GaN/substrate chip having the monocrystalline silicon thin-film on the SOI wafer and form a Si/SiN/AlGaN/GaN island and a SiN/AlGaN/GaN island on both sides of the isolation groove respectively;
employing an ion implantation process to implant phosphorus ions at a dose of 5×10 15 cm 2 and an energy of 30 keV onto the monocrystalline silicon thin-film of the Si/SiN/AlGaN/GaN island, and annealing under a nitrogen atmosphere at 1,000° C. for 60 s to activate impurities and form N-type heavily doped source and drain regions;
employing reactive ion etching and electron beam evaporation processes to etch away SiN on the source region on the SiN/AlGaN/GaN island, then depositing titanium metal with a thickness of 22 nm, aluminum metal with a thickness of 140 nm, nickel metal with a thickness of 55 nm and gold metal with a thickness of 45 nm sequentially on the source region to form a source electrode of a GaN high-electron-mobility transistor, and annealing under a nitrogen atmosphere with a temperature of 875° C. for 30 s, so that ohmic contact is formed between the source electrode and the AlGaN;
employing reactive ion etching and electron beam evaporation processes to etch away SiN on the gate and drain regions on the SiN/AlGaN/GaN island, and then sequentially depositing nickel metal with a thickness of 45-70 nm and gold metal with a thickness of 100-200 nm on the gate and drain regions after the SiN is etched away, so as to form a gate electrode and a drain electrode of the GaN high-electron-mobility transistor respectively;
employing an atomic layer deposition process to deposit aluminum sesquioxide with a thickness of 20-30 nm on the whole sample under conditions of a temperature of 300° C. and a nitrogen atmosphere, so as to form a gate dielectric layer of the Si metal oxide semiconductor field effect transistor; and then employing a magnetron sputtering process to spray tantalum nitride with a thickness of 100-200 nm on the aluminum sesquioxide thin-film above the undoped monocrystalline silicon thin-film, so as to form a gate electrode of the Si metal oxide semiconductor field effect transistor;
employing wet etching and electron beam evaporation processes to etch away aluminum sesquioxide on the source and drain regions of the monocrystalline silicon thin-film, depositing nickel metal with a thickness of 30-100 nm on the source and drain regions to form a source electrode and a

Assignees

• Univ Xidian

Inventors

• Zhang Chunfu
• Zhang Weihang
• Zhang Jiaqi
• Yang Guofang
• Wu Yichang
• Chen Dazheng
• Zhang Jincheng
• Hao Yue

Classifications

• H01L27/0883

  Electricity · mapped topic

• H01L27/0617

  Electricity · mapped topic

• H01L29/66462

  Electricity · mapped topic

• H01L29/778 Primary

  Electricity · mapped topic

• H10D84/84

  Combinations of enhancement-mode IGFETs and depletion-mode IGFETs · CPC title