SOI semiconductor structure and method for manufacturing an SOI semiconductor structure

Patent metadata

Field	Value
Publication number	US-11538855-B2
Application number	US-202117395536-A
Country	US
Kind code	B2
Filing date	Aug 6, 2021
Priority date	Nov 21, 2018
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

An SOI semiconductor structure, including a substrate layer formed on a back side and a semiconductor layer of a second conductivity type formed on a front side, an insulating layer being disposed between the substrate layer and the semiconductor layer, a three-dimensional Hall sensor structure having a sensor region made up of a monolithic semiconductor body being formed in the semiconductor layer, and the semiconductor body extending from an underside up to the front side, at least three first metallic terminal contacts being formed on the upper side, and at least three second metallic terminal contacts being formed on the underside, the first terminal contacts being offset with respect to the second terminal contacts in a projection perpendicular to the front side, each first terminal contact and each second terminal contact being formed in each case on a highly doped semiconductor contact region of a second conductivity type.

First claim

What is claimed is:

1. A method for manufacturing an SOI semiconductor structure, including a three-dimensional Hall sensor structure, the method comprising:
manufacturing, in a first process stage, at least three second highly doped semiconductor contact regions of a second conductivity type that are assigned to each of the second terminal contacts, via implantation in a plurality of process steps on a first front surface of a first semiconductor wafer, which includes a semiconductor layer having the first front surface and a first back surface;
joining, in a second process stage, the first front surface of the first semiconductor wafer to a second front surface of a second semiconductor wafer formed as a substrate layer;
forming an insulating layer between the first semiconductor wafer and the second semiconductor wafer after the joining, wherein, due to the joining, the first back surface of the first semiconductor wafer becomes a front side of the SOI semiconductor wafer, and the second back surface of the second semiconductor wafer becomes the back side of the SOI semiconductor wafer, and wherein the semiconductor surface of the first front surface of the first semiconductor wafer becomes a buried lower surface above the insulating layer after the joining;
thinning, in a third process stage, a front side of the first semiconductor wafer and highly doped first semiconductor contact regions are created via implantation; and
forming first terminal contacts on each of the first semiconductor contact regions.

2. The method for manufacturing an SOI semiconductor wafer according to claim 1 , wherein a trench structure completely surrounding the sensor region is formed on the front side in a fourth process stage.

3. The method for manufacturing an SOI semiconductor wafer according to claim 1 , wherein a doped polysilicon is deposited and structured during the first process stage for connecting the highly doped second semiconductor contact regions as second contact regions.

4. The method for manufacturing an Sal semiconductor wafer according to claim 1 , wherein the structured polysilicon is covered with the aid of a dielectric during the first process stage.

5. The method for manufacturing an SOI semiconductor wafer according to claim 1 , wherein an oxide is formed in the second process stage as an insulating layer.

6. The method for manufacturing an SOI semiconductor wafer according to claim 1 , wherein the semiconductor layer is formed with two different thicknesses in the third process stage, wherein the area of the sensor region has a greater thickness than the thickness of the area of the semiconductor layer surrounding the sensor region.

7. The method for manufacturing an SOI semiconductor wafer according to claim 1 , wherein a semiconductor layer having a thickness between 2 μm and 30 μm or less than 100 μm is formed in the third process stage via a CMP process.

8. The method for manufacturing an SOI semiconductor wafer according to claim 1 , wherein a semiconductor layer having a uniform thickness is formed in the third process stage.

9. The method for manufacturing an SOI semiconductor wafer according to claim 1 , wherein the trench etching outside the sensor region is carried out in the third process stage.

10. The method for manufacturing an SOI semiconductor wafer according to claim 1 , wherein the second buried terminal contacts are connected from the front side of the semiconductor layer in another process stage.

11. The method for manufacturing an SOI semiconductor wafer according to claim 1 , wherein the second terminal contacts are connected from the back side in another process stage.

12. The method for manufacturing an SOI semiconductor wafer according to claim 1 , wherein the first terminal contacts and the second terminal contacts are electrically connected to the integrated circuit in a fifth process stage.

Assignees

• Tdk Micronas Gmbh

Inventors

• Sander Christian
• Cornils Martin

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1914

  using bonding · CPC title

• H01L43/04

  Electricity · mapped topic

• H01L43/065

  Electricity · mapped topic

• H01L27/22 Primary

  Electricity · mapped topic