Coupled-line bus to suppress classical crosstalk for superconducting qubits

US11538854B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11538854-B2
Application numberUS-202016833479-A
CountryUS
Kind codeB2
Filing dateMar 27, 2020
Priority dateMar 27, 2020
Publication dateDec 27, 2022
Grant dateDec 27, 2022

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A system includes a first quantum circuit plane that includes a first qubit, a second qubit and a third qubit. A coupled-line bus is coupled between the first qubit and the second qubit. A second circuit plane is connected to the first quantum circuit plane, comprising a control line coupled to the third qubit. The control line and the coupled-line bus are on different planes and crossing over each other, and configured to mitigate cross-talk caused by the crossing during signal transmission.

First claim

Opening claim text (preview).

What is claimed is: 1. A system, comprising: a first quantum circuit plane comprising: a first qubit; a second qubit; a third qubit; and a coupled-line bus coupled between the first qubit and the second qubit; and a second circuit plane connected to the first quantum circuit plane, comprising a control line coupled to the third qubit, wherein the control line and the coupled-line bus are on different planes and cross over each other and are configured to mitigate cross-talk caused by the crossing over of the control line and the coupled-line during signal transmission. 2. The system of claim 1 , wherein the coupled-line bus is configured to transmit differential mode signals between the first and second qubits of the first quantum circuit plane. 3. The system of claim 1 , wherein the first quantum circuit plane and the second circuit plane are located on separate chips of a flip chip and connected together via bump bonds. 4. The system of claim 1 , wherein the control line is a feed line that is configured to transmit a signal to drive the third qubit. 5. The system of claim 1 , wherein the control line is a readout resonator that is configured to read a signal from the third qubit. 6. The system of claim 1 , wherein the control line is orthogonal to the coupled-line bus at the crossing over of the control line and the coupled-line bus to suppress an inductive coupling between the control line and the coupled-line bus. 7. The system of claim 1 , wherein the coupled-line bus is a dual strip coplanar waveguide (CPW) transmission-line resonator. 8. The system of claim 1 , wherein the first qubit and the second qubit are coupled to the coupled-line bus differentially and configured to excite only an odd mode of the coupled-line bus. 9. The system of claim 8 , wherein a cross talk from the control line to the coupled-line bus is configured to generate a common mode signal on the coupled-line bus that is electrically mitigated. 10. The system of claim 1 , wherein a suppression ratio of a crosstalk between the coupled-line bus and the control line depends on a gap between lines of the coupled-line bus. 11. A method of reducing crosstalk between different planes of qubits, the method comprising: providing a coupled-line bus between a first qubit and a second qubit of a first quantum circuit plane; providing a control line to a third qubit of the first quantum circuit plane, wherein the control line is on a second circuit plane that is on a different plane than the first quantum circuit plane; and coupling the first quantum circuit plane to the second circuit plane such that the control line and the coupled-line bus are on different planes and cross over each other, wherein the control line and the coupled-line bus mitigate cross talk caused by the crossing over of the control line and the coupled-line bus during signal transmission. 12. The method of claim 11 , further comprising transmitting differential mode signals between the first and second qubits of the first quantum circuit plane. 13. The method of claim 11 , wherein the first quantum circuit plane and the second circuit plane are located on separate chips and connected together via bump bonds. 14. The method of claim 11 , further comprising driving the third qubit through the control line. 15. The method of claim 11 , further comprising suppressing an inductive coupling between the control line and the coupled-line bus by arranging the control line to be orthogonal to the coupled-line bus. 16. The method of claim 11 , further comprising coupling the first qubit and the second qubit to the coupled-line bus differentially to excite only an odd mode of the coupled-line bus. 17. A quantum circuit structure, comprising: a coupled-line bus between a first qubit and a second qubit of a first quantum chip; and a control line to a third qubit, wherein: the control line that is on a second chip is on a different plane than the first quantum chip, the second chip is bonded to the first quantum chip via bump bonds, and the control line and the coupled-line bus are on different planes and cross over each other and configured to mitigate cross talk caused by the crossing over of the control line and the coupled-line bus during signal transmission. 18. The quantum circuit structure of claim 17 , wherein the coupled-line bus is configured to transmit differential mode signals between the first and second qubits of the first quantum chip. 19. The quantum circuit structure of claim 17 , wherein the control line is orthogonal to the coupled-line bus at the crossing to suppress an inductive coupling between the control line and the coupled-line bus. 20. The quantum circuit structure of claim 17 , wherein the first qubit and the second qubit are coupled to the coupled-line bus differentially and configured to excite only an odd mode of the coupled-line bus. 21. The quantum circuit structure of claim 17 , wherein a suppression ratio of a crosstalk between the coupled-line bus and the control line depends on a gap between lines of the coupled-line bus. 22. The quantum circuit structure of claim 17 , wherein the first qubit and the second qubit comprise additional coupling buses in addition to the coupled-line bus.

Assignees

Inventors

Classifications

  • Models of quantum computing, e.g. quantum circuits or universal quantum computers · CPC title

  • H01P3/026Primary

    Coplanar striplines [CPS] · CPC title

  • Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title

  • H01L27/18Primary

    Electricity · mapped topic

  • H10N69/00Primary

    Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00 · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11538854B2 cover?
A system includes a first quantum circuit plane that includes a first qubit, a second qubit and a third qubit. A coupled-line bus is coupled between the first qubit and the second qubit. A second circuit plane is connected to the first quantum circuit plane, comprising a control line coupled to the third qubit. The control line and the coupled-line bus are on different planes and crossing over …
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H01P3/026. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 27 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).