Power converter with an upper arm and a lower arm and at least first and second semiconductor devices connected by a bridging member

US11538794B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11538794-B2
Application numberUS-202016904088-A
CountryUS
Kind codeB2
Filing dateJun 17, 2020
Priority dateDec 19, 2017
Publication dateDec 27, 2022
Grant dateDec 27, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A power converter includes: at least one pair of first and second semiconductor devices including multiple first and second semiconductor chips, having first and second switching elements providing upper and lower arms, and multiple first and second main terminals having at least one of multiple first and second high potential terminals and multiple first and second low potential terminals; and a bridging member providing an upper and lower coupling portion, together with the first low and second high potential terminals. The first and second semiconductor chips are arranged in line symmetry with respect to first and second axes and in line symmetry with the second axis as a symmetry axis to differentiate the arrangement of the second low potential terminal with respect to the second high potential terminal from the arrangement of the first low potential terminal with respect to the first high potential terminal.

First claim

Opening claim text (preview).

What is claimed is: 1. A power converter comprising: an upper arm and a lower arm connected in series; the upper arm including at least one first semiconductor device that includes a plurality of first semiconductor chips, each of the plurality of first semiconductor chips has a first switching element, and a plurality of first main terminals which are connected to the plurality of first semiconductor chips and provide an electric connection function, the first switching elements being connected in parallel and the plurality of first main terminals including at least one first high potential terminal connected to an electrode of the first switching element on a high potential side and at least one first low potential terminal connected to an electrode of the first switching element on a low potential side; the lower arm including at least one second semiconductor device that includes a plurality of second semiconductor chips, each of the plurality of second conductor chips has a second switching element, and a plurality of second main terminals which are connected to the plurality of second semiconductor chips and provide an electric connection function, the second switching elements being connected in parallel, and the plurality of second main terminals including at least one second high potential terminal connected to an electrode of the second switching element on the high potential side and at least one second low potential terminal connected to an electrode of the second switching element on the low potential side; and a bridging member that bridges the at least one first low potential terminal and the at least one second high potential terminal, and provides an upper and lower coupling portion between the upper arm and the lower arm with the at least one first low potential terminal and the at least one second high potential terminal, wherein: in the at least one first semiconductor device, the plurality of first semiconductor chips are in line symmetry with respect to a first axis perpendicular to a first direction in which at least two of the plurality of first semiconductor chips are aligned, and the at least one first high potential terminal and the at least one first low potential terminal are each in line symmetry with respect to the first axis as a symmetry axis; and in the at least one second semiconductor device, the plurality of second semiconductor chips are in line symmetry with respect to a second axis perpendicular to a second direction in which at least two of the plurality of second semiconductor chips are aligned, the at least one second high potential terminal and the at least one second low potential terminal are each in line symmetry with respect to the second axis as the symmetry axis, and an arrangement of the at least one second low potential terminal relative to the at least one second high potential terminal is different from an arrangement of the at least one first low potential terminal relative to the at least one first high potential terminal. 2. The power converter according to claim 1 , wherein: there is an equal number of the first high potential terminals and the second low potential terminals; and there is an equal number of the first low potential terminals and the second high potential terminals. 3. The power converter according to claim 1 , wherein: a plurality of bridging members, the first low potential terminals and the second high potential terminals comprise a plurality of upper and lower coupling portions. 4. The power converter according to claim 3 , further comprising: a wiring portion configured to connect to a load, wherein: the wiring portion is drawn out from only a part of the plurality of the upper and lower coupling portions. 5. The power converter according to claim 4 , wherein: the wiring portion is not drawn out from each surface of the bridging member in a plate thickness direction, but is drawn out from an edge connecting two surfaces. 6. The power converter according to claim 5 , wherein: the wiring portion is drawn out from a place of the bridging member on a second high potential terminal side. 7. The power converter according to claim 3 , wherein: the plurality of the upper and lower coupling portions are provided by the bridging members having a same structure. 8. The power converter according to claim 1 , wherein: the first semiconductor device further includes a first sealing resin body that seals the plurality of first semiconductor chips; the second semiconductor device further includes a second sealing resin body that seals the plurality of second semiconductor chips; the plurality of first main terminals protrude from the first sealing resin body to an outside; the plurality of second main terminals protrude from the second sealing resin body to an outside; the bridging member connects a protruding portion of the at least one first low potential terminal and a protruding portion of the at least one second high potential terminal; the plurality of first main terminals protrude from a same surface of the first sealing resin body and are aligned along the first direction; and the plurality of second main terminals protrude from a same surface of the second sealing resin body and are aligned along the second direction. 9. The power converter according to claim 8 , wherein: the first main terminals include three first main terminals, the at least one first high potential terminal is between two of the at least on first low potential terminal; the second main terminals includes three second main terminals; and the at least one second low potential terminal is between two of the at least one second high potential terminal. 10. The power converter according to claim 1 , wherein: the first semiconductor device and the second semiconductor device are stacked such that the first semiconductor device and the second semiconductor device connected by the bridging member are adjacent; and at least one of a pair of the at least one first high potential terminal and the at least one second low potential terminal and a pair of the at least one first low potential terminal and the at least one second high potential terminal face each other at least partially in a stacking direction. 11. The power converter according to claim 10 , wherein: the at least one first semiconductor device includes a plurality of first semiconductor devices; the at least one second semiconductor device includes a plurality of second semiconductor devices; and the plurality of the first semiconductor devices and the plurality of the second semiconductor devices are alternately arranged. 12. The power converter according to claim 11 , further comprising: a smoothing capacitor that is configured to smooth a power supply voltage; a positive busbar that connects a positive electrode of the smoothing capacitor and the first high potential terminal; and a negative busbar that connects a negative electrode of the smoothing capacitor and the second low potential terminal, wherein: at least one of the positive busbar and the negative busbar has a plurality of through holes aligned side by side in the stacking direction; and the at least one first high potential terminal and the at least one second low potential terminal are individually in the through holes. 13. The power converter according to claim 10 , wherein: the at least one first semiconductor device includes a plurality of first semiconductor devices; and the at least one second semiconductor device includes a plurality of second semiconductor devices, the power converter further comprising: at least one of a por

Assignees

Inventors

Classifications

  • in a bridge configuration · CPC title

  • using discharge tubes with control electrode or semiconductor devices with control electrode · CPC title

  • for the simultaneous control of series or parallel connected semiconductor devices · CPC title

  • H02M7/003Primary

    Constructional details, e.g. physical layout, assembly, wiring or busbar connections · CPC title

  • Encapsulations, e.g. protective coatings · CPC title

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What does patent US11538794B2 cover?
A power converter includes: at least one pair of first and second semiconductor devices including multiple first and second semiconductor chips, having first and second switching elements providing upper and lower arms, and multiple first and second main terminals having at least one of multiple first and second high potential terminals and multiple first and second low potential terminals; and…
Who is the assignee on this patent?
Denso Corp
What technology area does this patent fall under?
Primary CPC classification H02M7/003. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 27 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).