Display panel and electronic apparatus

Patent metadata

Field	Value
Publication number	US-11538426-B2
Application number	US-202117452149-A
Country	US
Kind code	B2
Filing date	Oct 25, 2021
Priority date	Sep 19, 2019
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

A display panel includes a display area and a first peripheral area located around the display area. A first gate driver is provided in the first peripheral area. The display panel is further provided with a plurality of first driving signal lines and a plurality of second driving signal lines. The plurality of first driving signal lines are arranged in a different layer from a layer in which the plurality of second driving signal lines are located. The m-th first driving signal line of the plurality of first driving signal lines and the k-th second driving signal line of the plurality of second driving signal lines are both electrically connected, in the first peripheral area, to an m-th output terminal of the first gate driver, where m is an integer greater than or equal to 1 and k is also an integer greater than or equal to 1.

First claim

What is claimed is:

1. A display panel, comprising:
a display area; and
a first peripheral area located around the display area, a first gate driver being provided in the first peripheral area;
wherein the display panel is further provided with a plurality of first driving signal lines and a plurality of second driving signal lines;
wherein the plurality of first driving signal lines are arranged in a different layer from a layer in which the plurality of second driving signal lines are located; and
wherein an m-th first driving signal line of the plurality of first driving signal lines and a k-th second driving signal line of the plurality of second driving signal lines are both electrically connected, in the first peripheral area, to an m-th output terminal of the first gate driver, where m is an integer greater than or equal to 1 and k is also an integer greater than or equal to 1;
wherein the display panel further comprises a second peripheral area located around the display area; the first peripheral area and the second peripheral area are located at two opposite sides of the display area, respectively; and a second gate driver is provided in the second peripheral area; and the m-th first driving signal line of the plurality of first driving signal lines and the k-th second driving signal line of the plurality of second driving signal lines are both electrically connected, in the second peripheral area, to an m-th output terminal of the second gate driver; and
wherein the first driving signal line is a gate line, the second driving signal line is an auxiliary line, and a direction along which the first driving signal line extends is substantially parallel to a direction along which the second driving signal line extends.

2. The display panel according to claim 1 , wherein the display panel further comprises a base substrate, and an orthographic projection of the first driving signal line on the display panel at least partially overlaps with an orthographic projection of the second driving signal line on the display panel.

3. The display panel according to claim 1 , wherein a plurality of rows of sub-pixels are provided in the display area, and the gate lines and gate electrodes of transistors in the sub-pixel units are arranged in the same layer.

4. The display panel according to claim 1 , wherein the m-th first driving signal line is an m-th gate line that is electrically connected to the gate electrodes of the transistors in the m-th row of sub-pixel units.

5. The display panel according to claim 1 , wherein:
the display panel further comprises a base substrate, each of the first gate driver and the second gate driver comprises a semiconductor layer, and the k-th second driving signal line is a k-th auxiliary line that is located on a side of the semiconductor layer away from the base substrate; and
a planarization layer is provided on the side of the first gate driver and the second gate driver distal to the base substrate.

6. The display panel according to claim 5 , wherein the k-th auxiliary line is electrically connected to the m-th output terminal of the second gate driver through a second via hole.

7. The display panel according to claim 6 , wherein the second via hole is located in the peripheral area.

8. The display panel according to claim 7 , wherein the second via hole is located between the first gate driver and the display area, or the second via hole is located between the second gate driver and the display area.

9. The display panel according to claim 6 , wherein the display area further comprises:
a pixel definition layer on a side of the auxiliary lines distal to the base substrate;
an electron transport layer on a side of the pixel definition layer distal to the base substrate;
a cathode layer on a side of the electron transport layer distal to the base substrate;
a first passivation layer on a side of the cathode layer distal to the base substrate;
an encapsulation layer on a side of the first passivation layer distal to the base substrate; and
a second passivation layer on a side of the encapsulation layer distal to the base substrate.

10. The display panel according to claim 9 , wherein the first peripheral area further comprises:
a first level signal line, the first level signal line being further away from the display area than the first gate driver; and
a cathode connection layer on a side of the planarization layer distal to the base substrate,
wherein the cathode connection layer is electrically connected to the cathode layer and electrically connected to the first level signal line by an opening penetrating through the planarization layer.

11. The display panel according to claim 9 , wherein the second peripheral area further comprises:
a first level signal line, the first level signal line being further away from the display area than the second gate driver; and
a cathode connection layer on a side of the planarization layer distal to the base substrate,
wherein the cathode connection layer is electrically connected to the cathode layer and electrically connected to the first level signal line by an opening penetrating the planarization layer.

12. The display panel according to claim 1 , wherein:
a plurality of reset lines are further provided in the display area; and
an n-th output terminal of the first gate driver and an n-th output terminal of the second gate driver are both electrically connected to another reset line, where n is an integer greater than or equal to 2.

13. The display panel according to claim 10 , wherein each of the first peripheral area and the second peripheral area further comprises:
a first wall and a second wall which is farther from the display area than the first wall,
wherein the first wall comprises a first blocking layer on a side of the cathode connection layer distal to the base substrate and a second blocking layer on a side of the first blocking layer distal to the base substrate; the second wall comprises a third blocking layer on a side of the first level signal line distal to the base substrate, a fourth blocking layer on a side of the cathode connection layer distal to the base substrate, and a fifth blocking layer on a side of the fourth blocking layer distal to the base substrate; the first blocking layer and the fourth blocking layer are arranged in the same layer and made of the same material as the pixel definition layer; and the third blocking layer is arranged in the same layer and made of the same material as the planarization layer.

14. An electronic apparatus, comprising the display panel according to claim 1 .

15. The electronic apparatus according to claim 14 , wherein the auxiliary lines extend in a lateral direction, and the auxiliary lines have at least a protrusion in a longitudinal direction.

16. The electronic apparatus according to claim 14 , wherein the auxiliary lines have a fold-line shape.

Assignees

• Chongqing Boe Display Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wu Xinwei
• Zhang Zhen
• Zhang Wei
• Li Cunzhi
• Kwak Jonguk
• Xu Yanyan

Classifications

• G09G2320/0242

  Compensation of deficiencies in the appearance of colours · CPC title

• G09G3/2074 Primary

  using sub-pixels · CPC title

• G09G3/3607 Primary

  for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels (display of colours in flat matrix panels other than liquid crystal displays G09G3/2003; grey scales specific for television H04N3/127) · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2320/0666

  for control of colour parameters, e.g. colour temperature · CPC title