Dual cast mirroring from host devices

Patent metadata

Field	Value
Publication number	US-11537313-B1
Application number	US-202117399129-A
Country	US
Kind code	B1
Filing date	Aug 11, 2021
Priority date	Aug 11, 2021
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

Mirrored volatile memory in a storage system is configured with a dual cast region of addresses. Buffers in the dual cast region are allocated for data associated with a received Write IO. A host IO device associates the dual cast addresses with the data. A switch or CPU complex recognizes the dual cast addresses associated with the data and, in response, creates and sends a first copy of the data to a first volatile memory mirror and creates and sends a second copy of the data to a second volatile memory mirror. The second copy may be sent via PCIe NTB between switches or CPU complexes.

First claim

What is claimed is:

1. A storage system comprising:
a first compute node comprising at least one processor;
a first mirrored volatile memory in communication with the first compute node;
a second compute node comprising at least one processor, the second compute node configured in a failover relationship with the first compute node;
a second mirrored volatile memory in communication with the first compute node and configured to mirror the first volatile memory;
a host IO device in communication with a host and the first compute node; and
dual casting logic configured to create and send a first copy of data associated with a write command to the first mirrored volatile memory and send a second copy of the data to the second mirrored volatile memory before the first copy of the data is written to the first mirrored volatile memory and without reading the data from either the first mirrored volatile memory or the second mirrored volatile memory.

2. The storage system of claim 1 wherein the first volatile memory and the second volatile memory comprise a dual cast region of buffer addresses.

3. The storage system of claim 2 wherein the host IO device is configured to cause the data to be dual casted to both the first volatile memory and the second volatile memory based on an allocated buffer address for the data being in the dual cast region.

4. The storage system of claim 3 wherein the dual cast region is defined by a range of addresses.

5. The storage system of claim 1 comprising a communication link between the first compute node and the second compute node that is used for dual casting.

6. The storage system of claim 1 further comprising a first switch connected between the host IO device and the first compute node, and a second switch connected to the second compute node, and comprising a communication link between the first switch and the second switch that is used for dual casting.

7. The storage system of claim 6 wherein the communication link comprises a Peripheral Component Interconnect Express (PCIe) Non-Transparent Bridge (NTB).

8. A mirroring method implemented in a storage system that includes a first compute node, a first mirrored volatile memory in communication with the first compute node, a second compute node configured in a failover relationship with the first compute node, a second mirrored volatile memory in communication with the first compute node and configured to mirror the first mirrored volatile memory, and a host IO device in communication with a host and the first compute node, the method comprising:
allocating buffers in a region of dual cast addresses of the first mirrored volatile memory and the second mirrored volatile memory;
associating the dual cast addresses with received Write IO data; and
responsive to recognition that the data is associated with dual cast addresses, creating and sending a first copy of the data to the first mirrored volatile memory and creating and sending a second copy of the data to the second mirrored volatile memory before the first copy of the data is written to the first volatile memory and without reading the data from either the first mirrored volatile memory or the second mirrored volatile memory.

9. The method of claim 8 comprising a host IO device associating the dual cast addresses with received Write IO data.

10. The method of claim 9 comprising the first compute node recognizing that the data is associated with dual cast addresses.

11. The method of claim 10 comprising the first compute node sending the first copy of the data to the first volatile memory and sending the second copy of the data to the second volatile memory.

12. The method of claim 11 comprising the first compute node sending the second copy of the data to the second volatile memory via a Peripheral Component Interconnect Express (PCIe) Non-Transparent Bridge (NTB) between the first compute node and the second compute node.

13. The method of claim 9 comprising a first PCIe switch recognizing that the data is associated with dual cast addresses.

14. The method of claim 13 comprising the first PCIe switch sending the first copy of the data to the first volatile memory and sending the second copy of the data to the second volatile memory.

15. The method of claim 14 comprising the first PCIe switch sending the second copy of the data to the second volatile memory via a PCIe Non-Transparent Bridge (NTB) between the first PCIe switch and a second PCIe switch.

16. A non-transitory computer-readable storage medium storing instructions that when executed by a storage system cause the storage system to perform a method for mirroring, the method comprising:
allocating buffers in a region of dual cast addresses of a first mirrored volatile memory and a second mirrored volatile memory configured to mirror the first mirrored volatile memory;
associating the dual cast addresses with received Write IO data; and
responsive to recognition that the data is associated with dual cast addresses, creating and sending a first copy of the data to the first mirrored volatile memory and creating and sending a second copy of the data to the second mirrored volatile memory before the first copy of the data is written to the first mirrored volatile memory and without reading the data from either the first mirrored volatile memory or the second mirrored volatile memory.

17. The non-transitory computer-readable storage medium of claim 16 wherein the method comprises a host IO device associating the dual cast addresses with received Write IO data.

18. The non-transitory computer-readable storage medium of claim 17 wherein the method comprises a first compute node recognizing that the data is associated with dual cast addresses and creating and sending the first copy of the data to the first volatile memory and creating and sending the second copy of the data to the second volatile memory.

19. The non-transitory computer-readable storage medium of claim 18 wherein the method comprises the first compute node sending the second copy of the data to the second volatile memory via a Peripheral Component Interconnect Express (PCIe) Non-Transparent Bridge (NTB) between the first compute node and a second compute node.

20. The non-transitory computer-readable storage medium of claim 17 wherein the method comprises a first PCIe switch recognizing that the data is associated with dual cast addresses and creating and sending the first copy of the data to the first volatile memory and creating and sending the second copy of the data to the second volatile memory.

Assignees

• Emc Ip Holding Co Llc

Inventors

• Duquette Jason J
• Guyer James M
• Mackintosh Thomas
• Medeiros Earl

Classifications

• G06F3/065 Primary

  Replication mechanisms · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F3/0613

  in relation to throughput · CPC title

• G06F3/067

  Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS] · CPC title