Wafer carrier and method

Patent metadata

Field	Value
Publication number	US-11535952-B2
Application number	US-202017030727-A
Country	US
Kind code	B2
Filing date	Sep 24, 2020
Priority date	Apr 3, 2017
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

A wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket having a base and a substantially circular perimeter, and a removable orientation marker, the removable orientation marker comprising an outer surface and an inner surface, the outer surface having an arcuate form sized and shaped to mate with the substantially circular perimeter of the pocket, and the inner surface comprising a flat face, wherein the removable orientation marker further comprises a notch at a first end of the flat face.

First claim

What is claimed is:

1. A method, comprising:
placing a wafer in a wafer carrier comprising a pocket sized and shaped to accommodate a wafer, the pocket being defined by a base and a substantially circular peripheral wall comprising an inner face and an outer face, wherein a notch in the inner face of the substantially circular peripheral wall provides a localised increased gap between the inner face and a side face of the wafer, the wafer carrier having a predetermined direction of rotation about an axis positioned perpendicular to an upper surface of the base of the pocket;
rotating the wafer carrier in the predetermined direction of rotation; and
epitaxially depositing a semiconductor layer on the wafer while rotating the wafer carrier in the predetermined direction of rotation,
wherein the notch comprises a base having a first radius r 1 , a first lip transitioning between the substantially circular perimeter and the base of the notch and having a second radius r 2 , and a second lip transitioning between the substantially circular perimeter and the base of the notch and having a third radius r 3 ,
wherein a center point of the first radius r 1 lies radially inwardly of the inner face and center points of the second and third radii r 2 and r 3 lies radially outwardly of the inner face such that the notch has an s-shaped contour.

2. The method of claim 1 , wherein the semiconductor layer comprises a Group III nitride.

3. The method of claim 2 , wherein the wafer is selected from the group consisting of <100> Si, <111> Si, Sapphire and SiC.

4. The method of claim 1 , further comprising heating the wafer carrier to a temperature of at least 600° C., and wherein the semiconductor layer is epitaxially deposited on the wafer at a temperature of at least 600° C. while rotating the wafer carrier in the predetermined direction of rotation.

5. The method of claim 1 , wherein the inner face includes a flat face and an arcuate face.

6. A method, comprising:
placing a wafer in a wafer carrier comprising a pocket sized and shaped to accommodate a wafer, the pocket being defined by a base and a substantially circular peripheral wall comprising an inner face and an outer face, wherein a notch in the inner face of the substantially circular peripheral wall provides a localised increased gap between the inner face and a side face of the wafer, the wafer carrier having a predetermined direction of rotation about an axis positioned perpendicular to an upper surface of the base of the pocket;
rotating the wafer carrier in the predetermined direction of rotation; and
epitaxially depositing a semiconductor layer on the wafer while rotating the wafer carrier in the predetermined direction of rotation,
wherein the inner face includes a flat face and an arcuate face,
wherein the notch is arranged at a transition between the flat face and the arcuate face of the inner face,
wherein the notch comprises a base having a first radius r 1 , a first lip transitioning between the substantially circular perimeter and the base of the notch and having a second radius r 2 , and a second lip transitioning between the substantially circular perimeter and the base of the notch and having a third radius r 3 ,
wherein a center point of the first radius r 1 lies radially inwardly of the inner face and center points of the second and third radii r 2 and r 3 lies radially outwardly of the inner face such that the notch has an s-shaped contour.

7. The method of claim 6 , wherein the semiconductor layer comprises a Group III nitride.

8. The method of claim 7 , wherein the wafer is selected from the group consisting of <100> Si, <111> Si, Sapphire and SiC.

9. The method of claim 6 , further comprising heating the wafer carrier to a temperature of at least 600° C., and wherein the semiconductor layer is epitaxially deposited on the wafer at a temperature of at least 600° C. while rotating the wafer carrier in the predetermined direction of rotation.

10. The method of claim 6 , wherein the notch is positioned at a trailing edge of the flat face with respect to the predetermined direction of rotation.

11. The method of claim 6 , further comprising a further notch that is arranged at the opposite end of the flat face.

12. The method of claim 6 , wherein the wafer includes a wafer flat face, a wafer arcuate face, and an interface between the wafer flat face and the wafer arcuate face, and wherein the interface is positioned within the notch.

13. The method of claim 6 , wherein the wafer includes a wafer flat face, and wherein the wafer flat face is in contact with the second lip.

Assignees

• Infineon Technologies Americas Corp

Inventors

• Tungare Mihir
• Kim Peter
• Wan Jianwei
• Choi Chankyung

Classifications

• C30B25/02

  Epitaxial-layer growth · CPC title

• C23C16/4584

  the substrate being rotated · CPC title

• C30B29/06

  Silicon · CPC title

• C30B25/12 Primary

  Substrate holders or susceptors · CPC title

• C23C16/303

  Nitrides · CPC title