Micro-channel device and manufacturing method thereof and micro-fluidic system

US11534755B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11534755-B2
Application numberUS-201916755911-A
CountryUS
Kind codeB2
Filing dateApr 16, 2019
Priority dateApr 16, 2019
Publication dateDec 27, 2022
Grant dateDec 27, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure relates to a micro-channel device. The micro-channel device may include a micro-channel structure and a semiconductor junction. The micro-channel structure may include a base layer, a plurality of rails distributed on the base layer at intervals, and a cover layer comprising a plurality of columns. The cover layer and the base layer are configured to form a plurality of micro-channels. The semiconductor junction may include a P-type semiconductor layer, an intrinsic semiconductor layer and a N-type semiconductor layer stacked in a first direction.

First claim

Opening claim text (preview).

What is claimed is: 1. A micro-channel device, comprising: a micro-channel structure comprising a base layer, a plurality of rails distributed on the base layer at intervals, and a cover layer comprising a plurality of columns, wherein the cover layer and the base layer are configured to form a plurality of micro-channels, the cover layer covers the plurality of rails, each of the plurality of micro-channels is formed between two adjacent rails, and the plurality of rails and the plurality of micro-channels are arranged alternatively; and a semiconductor junction comprising a P-type semiconductor layer, an intrinsic semiconductor layer and a N-type semiconductor layer, wherein the P-type semiconductor layer, the intrinsic semiconductor layer, and the N-type semiconductor layer are placed together, the base layer and the cover layer are placed together, the micro-channel structure and the semiconductor junction form an integrated structure; wherein the plurality of columns and the plurality of rails have a one-to-one correspondence, and each of the plurality of columns has a ridge formed at a position corresponding to one of the plurality of rails; and the N-type semiconductor layer is the base layer of the micro-channel structure, the plurality of rails is directly formed on the base layer, the plurality of rails is made of the same material as the base layer, the cover layer is in physical contact with the N-type semiconductor layer, and the cover layer is made of a transparent conductive material. 2. The micro-channel device of claim 1 , wherein an orthographic projection of one of the plurality of columns on the base layer covers an orthographic projection of a corresponding rail on the base layer. 3. The micro-channel device of claim 1 , wherein each of the plurality of rails extends along a second direction, and the plurality of micro-channels have a same extension direction as the second direction. 4. The micro-channel device of claim 1 , wherein at least one of the plurality of rails has a S-shape, and a corresponding column has the same S-shape. 5. The micro-channel structure of claim 1 , wherein the P-type semiconductor layer, the intrinsic semiconductor layer, and the N-type semiconductor layer are stacked in a first direction on a base substrate, and the first direction is perpendicular to the base substrate. 6. The micro-channel device of claim 1 , wherein a distance between each of the plurality of rails ranges from 10 nm to 1 μm. 7. The micro-channel device of claim 1 , wherein each of the plurality of rails has a height between approximately 10 nm to 300 nm. 8. A micro-fluidic system, comprising the micro-channel device of claim 1 . 9. A method of manufacturing a micro-channel device, comprising: forming a micro-channel structure comprising a base layer, a plurality of rails distributed on the base layer at intervals, and a cover layer comprising a plurality of columns: and integrating a semiconductor junction with the micro-channel structure wherein the cover layer and the base layer are configured to form a plurality of micro-channels, the cover layer covers the plurality of rails, each of the plurality of micro-channels is formed between two adjacent rails, and the plurality of rails and the plurality of micro-channels are arranged alternatively; the semiconductor junction comprises a P-type semiconductor layer, an intrinsic semiconductor layer and a N-type semiconductor layer stacked in a first direction; and the plurality of columns and the plurality of rails have a one-to-one correspondence, and each of the plurality of columns has a ridge formed at a position corresponding to one of the plurality of rails. 10. The method of manufacturing the micro-channel device of claim 9 , wherein the N-type semiconductor layer is patterned to form the plurality of rails distributed on a surface of the N-type semiconductor layer, wherein the base layer is the N-type semiconductor. 11. The method of manufacturing the micro-channel device of claim 10 , wherein the plurality of columns is formed by sputtering a transparent conductive material on the plurality of rails.

Assignees

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Classifications

  • Specific details about materials · CPC title

  • Laminated structure · CPC title

  • characterised by the manufacture of the container or its components · CPC title

  • characterised by interfacing components, e.g. fluidic, electrical, optical or mechanical interfaces · CPC title

  • Specific details about manufacturing devices · CPC title

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What does patent US11534755B2 cover?
The present disclosure relates to a micro-channel device. The micro-channel device may include a micro-channel structure and a semiconductor junction. The micro-channel structure may include a base layer, a plurality of rails distributed on the base layer at intervals, and a cover layer comprising a plurality of columns. The cover layer and the base layer are configured to form a plurality of m…
Who is the assignee on this patent?
Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification B01L3/502707. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Dec 27 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).