Analog-to-digital converter system, transceiver, base station and mobile device

Patent metadata

Field	Value
Publication number	US-11528182-B2
Application number	US-202117351288-A
Country	US
Kind code	B2
Filing date	Jun 18, 2021
Priority date	Dec 23, 2019
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.

First claim

What is claimed is:

1. An Analog-to-Digital Converter, ADC, system, comprising:
a first ADC circuit;
at least one second ADC circuit;
a first input for receiving a transmit signal of a transceiver, wherein the first ADC circuit is coupled to the first input and configured to provide first digital data based on the transmit signal;
a second input for receiving a receive signal of the transceiver, wherein the at least one second ADC circuit is coupled to the second input, and wherein the at least one second ADC circuit is configured to provide second digital data based on the receive signal;
a first output configured to output digital feedback data based on the first digital data;
a second output configured to output digital receive data based on the second digital data; and
common calibration control circuitry configured to supply respective calibration data to the first ADC circuit and the at least one second ADC circuit in order to linearize the first ADC circuit and the at least one second ADC circuit.

2. The ADC system of claim 1 , further comprising common clock distribution circuitry configured to supply a respective clock signal to the first ADC circuit and the at least one second ADC circuit.

3. The ADC system of claim 1 , further comprising common reference voltage generation circuitry configured to supply a respective reference voltage to the first ADC circuit and the at least one second ADC circuit.

4. The ADC system of claim 1 , further comprising common biasing circuitry configured to supply a respective bias to the first ADC circuit and the at least one second ADC circuit.

5. The ADC system of claim 1 , further comprising common synchronization circuitry configured to synchronize the first digital data and the second digital data.

6. The ADC system of claim 1 , further comprising common calibration circuitry configured to generate the digital feedback data and the digital receive data by calibrating the first digital data and the second digital data.

7. The ADC system of claim 1 , further comprising common calibration signal circuitry configured to supply a respective calibration signal to the first ADC circuit and the at least one second ADC circuit.

8. The ADC system of claim 1 , wherein the first ADC circuit and the at least one second ADC circuit are implemented identical.

9. The ADC system of claim 1 , wherein the first ADC circuit and the at least one second ADC circuit are physically arranged in an array, and wherein the first ADC circuit is physically arranged at an edge of the array.

10. The ADC system of claim 1 , wherein the ADC system comprises a plurality of second ADC circuits, the plurality of second ADC circuits being time-interleaved.

11. A transceiver, comprising:
an ADC system according to claim 1 ;
a transmit path configured to generate the transmit signal, wherein the first input is coupled to the transmit path; and
digital receive circuitry configured to process the digital receive data.

12. The transceiver of claim 11 , further comprising digital pre-distortion circuitry configured to receive the digital feedback data from the ADC system for training a pre-distortion model for pre-distorting digital transmit data.

13. The transceiver of claim 12 , wherein the transmit path is configured to generate the transmit signal based on the digital transmit data.

14. The transceiver of claim 11 , wherein the first input is coupled to the transmit path via a filter.

15. The transceiver of claim 11 , wherein the first input is coupled to the transmit path via a buffer circuit.

16. The transceiver of claim 11 , wherein the first input is coupled to the transmit path via a scaling circuit configured to scale the transmit signal.

17. A base station, comprising:
transceiver according to claim 11 ; and
at least one antenna element coupled to the transceiver.

18. The base station of claim 17 , wherein the receive signal is received by the antenna element.

19. A mobile device, comprising:
transceiver according to claim 11 ; and
at least one antenna element coupled to the transceiver.

Assignees

• Intel Corp

Inventors

• Azadet Kameran
• Clara Martin
• Gruber Daniel
• Lindholm Christian
• Shin Hundo

Classifications

• H04B2001/0425

  with linearisation using predistortion · CPC title

• H03M1/0602

  of deviations from the desired transfer characteristic (H03M1/0617 takes precedence) · CPC title

• H03M1/1215 Primary

  using time-division multiplexing · CPC title

• H04B1/0475

  with means for limiting noise, interference or distortion (H04B1/0483 takes precedence) · CPC title

• H03M1/1009

  Calibration · CPC title