Oscillator circuit having low jitter and insensitivity to temperature changes

Patent metadata

Field	Value
Publication number	US-11527993-B2
Application number	US-202117218983-A
Country	US
Kind code	B2
Filing date	Mar 31, 2021
Priority date	Nov 25, 2020
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

An oscillator circuit includes an initial level setting circuit configured to operate in an on-state during an initial operation of the oscillator circuit to supply a first level voltage to a first node and a second level voltage to a second node, a switching circuit configured to connect a power supply voltage terminal and a ground terminal to the first or second node in response to first and second clock signals having different phases after the initial operation, a signal generation circuit connected between the first and second nodes and configured to perform charging and discharging operations based on a potential difference between the first and second nodes, and generate first and second voltages determined by the charging and discharging operations, and an inverter circuit configured to generate the first clock signal based on the first voltage, and generate the second clock signal based on the second voltage.

First claim

What is claimed is:

1. An oscillator circuit comprising:
an initial level setting circuit configured to operate in an on-state during an initial operation of the oscillator circuit to supply a first level voltage to a first node and a second level voltage to a second node;
a switching circuit configured to connect a power supply voltage terminal and a ground terminal to the first node or the second node in response to a first clock signal and a second clock signal having different phases after the initial operation of the oscillator circuit;
a signal generation circuit connected between the first node and the second node and configured to perform a charging operation and a discharging operation based on a potential difference between the first node and the second node, and generate a first voltage and a second voltage determined by the charging operation and the discharging operation; and
an inverter circuit configured to generate the first clock signal based on the first voltage, and generate the second clock signal based on the second voltage.

2. The oscillator circuit of claim 1 , wherein the initial level setting circuit is further configured to operate in an off-state after the initial operation of the oscillator circuit to not supply the first level voltage to the first node and not supply the second level voltage to the second node.

3. The oscillator circuit of claim 1 , wherein the initial level setting circuit comprises:
a first initial level setting unit configured to operate in an on-state during the initial operation of the oscillator circuit to supply the first level voltage to the first node; and
a second initial level setting unit configured to operate in an on-state during the initial operation of the oscillator circuit to supply the second level voltage to the second node.

4. The oscillator circuit of claim 1 , wherein the switching circuit comprises:
a first switch configured to alternately connect the power supply voltage terminal to the first node and the second node in response to the first clock signal; and
a second switch configured to alternately connect the ground terminal to the second node and the first node in response to the second clock signal.

5. The oscillator circuit of claim 4 , wherein the first switch and the second switch are further configured so that the first switch connects the power supply voltage terminal to the first node while the second switch connects the ground terminal to the second node, and the first switch connects the ground terminal to the second node while the second switch connects the power supply voltage terminal to the first node.

6. The oscillator circuit of claim 1 , wherein the signal generation circuit comprises:
a first RC circuit comprising a first resistor and a first capacitor connected in series between the first node and the second node to perform a charging operation and a discharging operation based on the potential difference between the first node and the second node, and output the first voltage from an intermediate connection node between the first resistor and the first capacitor; and
a second RC circuit comprising a second capacitor and a second resistor connected in series between the first node and the second node to perform a charging operation and a discharging operation based on the potential difference between the first node and the second node, and output the second voltage from an intermediate connection node between the second capacitor and the second resistor.

7. The oscillator circuit of claim 6 , wherein a time constant of the first resistor and the first capacitor of the first RC circuit determines an oscillation frequency of the first clock signal, and
a time constant of the second capacitor and the second resistor of the second RC circuit determines an oscillation frequency of the second clock signal.

8. The oscillator circuit of claim 1 , wherein the inverter circuit comprises:
a first inverter configured to generate the first clock signal by inverting the first voltage; and
a second inverter configured to generate the second clock signal by inverting the second voltage.

9. The oscillator circuit of claim 8 , wherein the first inverter is further configured to generate the first clock signal by inverting the first voltage based on a first threshold voltage,
the second inverter is further configured to generate the second clock signal by inverting the second voltage based on a second threshold voltage different from the first threshold voltage,
the first threshold voltage causes the first clock signal to have an on-duty ratio of less than 50%, and
the second threshold voltage causes the second clock signal to have an on-duty ratio of greater than 50%.

10. An oscillator circuit comprising:
an initial level setting circuit configured to operate in an on-state in response to a control signal during an initial operation of the oscillator circuit to supply a first level voltage to a first node and a second level voltage to a second node;
a switching circuit configured to connect a power supply voltage terminal and a ground terminal to the first node or the second node in response to a first clock signal and a second clock signal having different phases after the initial operation of the oscillation circuit;
a signal generation circuit connected between the first node and the second node and configured to perform a charging operation and a discharging operation based on a potential difference between the first node and the second node, and generate a first voltage and a second voltage determined by the charging operation and the discharging operation;
an inverter circuit configured to generate the first clock signal based on the first voltage, and generate the second clock signal based on the second voltage; and
a control circuit configured to generate the control signal to control the initial level setting circuit to operate in the on-state during the initial operation of the oscillator circuit.

11. The oscillator circuit of claim 10 , wherein the initial level setting circuit is further configured to operate in an off-state in response to the control signal after the initial operation of the oscillator circuit to not supply the first level voltage to the first node and not supply the second level voltage to the second node, and
the control circuit is further configured to generate the control signal to control the initial level setting circuit to operate in the off-state after the initial operation of the oscillator circuit.

12. The oscillator circuit of claim 10 , wherein the initial level setting circuit comprises:
a first initial level setting unit configured to operate in an on-state during the initial operation of the oscillator circuit to supply the first level voltage to the first node; and
a second initial level setting unit configured to operate in an on-state during the initial operation of the oscillator circuit to supply the second level voltage to the second node.

13. The oscillator circuit of claim 10 , wherein the switching circuit comprises:
a first switch configured to alternately connect the power supply voltage terminal to the first node and the second node in response to the first clock signal; and
a second switch configured to alternately connect the ground terminal to the second node and the first node in response to the second clock signal.

14. The oscillator circuit of claim 13 , wherein the first switch and the second switch are further configured so that the first switch connects the power supply voltage terminal to the first node while the second switch connects the ground terminal to the seco

Assignees

• Samsung Electro Mech

Inventors

• Kim Myeung Su

Classifications

• H04N25/75

  Circuitry for providing, modifying or processing image signals from the pixel array · CPC title

• H04N25/70

  SSIS architectures; Circuits associated therewith · CPC title

• H03B5/04 Primary

  Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature · CPC title

• H03K3/011 Primary

  Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature {(to maintain energy constant H03K3/015)} · CPC title

• H03K3/0231

  Astable circuits {(H03K3/0315 takes precedence)} · CPC title