Method of texturing semiconductor substrate, semiconductor substrate manufactured using the method, and solar cell including the semiconductor substrate

Patent metadata

Field	Value
Publication number	US-11527673-B2
Application number	US-201716333252-A
Country	US
Kind code	B2
Filing date	Nov 1, 2017
Priority date	Sep 14, 2017
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

An embodiment includes a method of texturing a semiconductor substrate, a semiconductor substrate manufactured using the method, and a solar cell including the semiconductor substrate, the method including: forming metal nanoparticles on a semiconductor substrate, primarily etching the semiconductor substrate, removing the metal nanoparticles, and secondarily etching the primarily etched semiconductor substrate to form nanostructures.

First claim

What is claimed is:

1. A method of texturing a semiconductor substrate, the method comprising:
depositing a dielectric thin film on a semiconductor substrate;
forming metal nanoparticles on the semiconductor substrate;
primarily etching the semiconductor substrate;
removing the metal nanoparticles; and
secondarily etching the primarily etched semiconductor substrate to form nanostructures;
wherein the forming of the metal nanoparticles comprises forming the metal nanoparticles on the dielectric thin film at room temperature without an annealing process using a physical vapor deposition by applying bimodal growth process of simultaneously growing large metal nanoparticles and small metal nanoparticles,
the primary etching of the semiconductor substrate comprises etching the dielectric thin film and the semiconductor substrate to pattern the dielectric thin film on the semiconductor substrate,
the removing of the metal nanoparticles comprises removing the metal nanoparticles formed on the dielectric thin film, and
the secondary etching of the primarily etched semiconductor substrate comprises etching the dielectric thin film patterned during the primary etching of the semiconductor substrate and the semiconductor substrate etched during the primary etching of the semiconductor substrate to form nanostructures.

2. The method of claim 1 , wherein the semiconductor substrate is formed of a crystalline silicon wafer, and
the secondary etching of the primarily etched semiconductor substrate comprises etching the dielectric thin film patterned during the primary etching of the semiconductor substrate and the semiconductor substrate etched during the primary etching of the semiconductor substrate to form silicon nanostructures having a pyramid shape or an elliptical hole shape.

3. The method of claim 1 , wherein the secondary etching of the primarily etched semiconductor substrate comprises etching the dielectric thin film patterned during the primary etching of the semiconductor substrate and the semiconductor substrate etched during the primary etching of the semiconductor substrate to form nanostructures, and
the nanostructures are formed to have a depth of 100 nm to 1000 nm.

4. The method of claim 1 , wherein the dielectric thin film comprises a silicon-based nitride, a silicon-based oxide, a silicon oxynitride, or an aluminum-based oxide and is a type of single layer or multilayered thin film.

5. The method of claim 1 , wherein the dielectric thin film has a thickness of 50 nm to 400 nm.

6. The method of claim 1 , wherein the metal nanoparticles are formed of indium (In), tin (Sn), or an In—Sn alloy which has a melting point of 250° C. or lower.

7. The method of claim 1 , wherein a nominal thickness of the metal nanoparticles ranges from 50 nm to 200 nm.

8. The method of claim 1 , wherein a size of the small metal nanoparticles generated using the bimodal growth process is more than 0% of a size of the large metal nanoparticles and equal to or less than 50% of the size of the large metal nanoparticles, and an average diameter of the large metal nanoparticles is more than 0 nm and equal to or less than 1,000 nm.

9. The method of claim 1 , wherein the primary etching of the semiconductor substrate comprises etching the dielectric thin film and the semiconductor substrate to pattern the dielectric thin film on the semiconductor substrate, and
the dielectric thin film and the semiconductor substrate are etched to have a depth of 100 nm to 500 nm.

10. The method of claim 1 , wherein the secondary etching of the primarily etched semiconductor substrate comprises wet etching the semiconductor substrate by using the dielectric thin film, which is patterned during the primary etching of the semiconductor substrate, and a solution including any one of hydrogen fluoride, nitric acid, acetic acid, and phosphoric acid or a mixture of at least two thereof, and forming nanostructures having an elliptical hole shape.

Assignees

• Korea Inst Sci & Tech

Inventors

• Lee Doh Kwon
• Kim In Ho
• Kim Won Mok
• Park Jong Keuk
• Lee Taek Sung
• Jeong Doo Seok
• Lee Hyeon Seung
• Jeong Jeung Hyun

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P76/2041

  Photolithographic processes · CPC title

• H10P14/3461

  Nanoparticles · CPC title

• Y02E10/52

  PV systems with concentrators · CPC title

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title