Precision structured glass articles, integrated circuit packages, optical devices, microfluidic devices, and methods for making the same

Patent metadata

Field	Value
Publication number	US-11527452-B2
Application number	US-202217743643-A
Country	US
Kind code	B2
Filing date	May 13, 2022
Priority date	Jul 24, 2017
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

The present disclosure relates to a reconstituted wafer- and/or panel-level package comprising a glass substrate having a plurality of cavities. Each cavity is configured to hold a single IC chip. The reconstituted wafer- and/or panel-level package can be used in a fan-out wafer or panel level packaging process. The glass substrate can include at least two layers having different photosensitivities with one layer being sufficiently photosensitive to be capable of being photomachined to form the cavities.

First claim

The invention claimed is:

1. A structured glass article, comprising:
a glass substrate comprising a glass cladding layer fused to a glass base layer; and
one or more cavities formed in the glass cladding layer, each cavity extending from a surface of the glass cladding layer and having a depth,
wherein the glass base layer defines a floor of each cavity and the glass cladding layer defines one or more sidewalls of each cavity, and
wherein a distance across each cavity between opposed portions of the one or more sidewalls, when measured at a first depth proximate the surface and at a second depth proximate the floor, differs by at most 1 mm in a direction normal to the depth.

2. The structured glass article of claim 1 , wherein the glass cladding layer has a higher etch rate in an etchant than the glass core layer.

3. The structured glass article of claim 1 , wherein a first photosensitivity of the glass cladding layer is greater than a second photosensitivity of the glass base layer.

4. The structured glass article of claim 1 , wherein the distance across each cavity passes through a centroid of the cavity at the first and second depths.

5. The structured glass article of claim 1 , wherein the floor of the one or more cavities comprises a surface roughness of at most about 20 nm.

6. The structured glass article of claim 1 , wherein the depth of each cavity comprises a third depth at a first position along a perimeter of the cavity and a fourth depth at a second position along the perimeter of the cavity opposite the first position, the third depth and the fourth depth differing by at most about 5μm.

7. The structured glass article of claim 1 , wherein the depth of each cavity corresponds to a thickness of the glass cladding layer.

8. The structured glass article of claim 1 , wherein an angle formed between the one or more sidewalls and the floor of each cavity is at most about 30°.

9. The structured glass article of claim 1 , wherein the distance across each cavity corresponds to a width of each cavity and a difference between a first width at a top of the cavity and a second width at a bottom of the cavity is at most about 1 mm in a direction normal to the depth.

10. The structured glass article of claim 9 , wherein the depth of each cavity is at least about 50 μm.

11. A packaged integrated circuit, comprising:
a structured glass article comprising a glass cladding layer fused to a glass base layer and a cavity formed in the glass cladding layer, the cavity extending from a surface of the glass cladding layer and having a depth, the glass base layer defining a floor of the cavity and the glass cladding layer defining one or more sidewalls of the cavity; and
an integrated circuit chip disposed within the cavity, the integrated circuit chip having a peripheral surface that faces the one or more sidewalls of the cavity,
wherein a gap between the peripheral surface and the one or more sidewalls is no more than 20 μm in a direction normal to the depth.

12. The packaged integrated circuit of claim 11 , wherein the depth of the cavity is no more than 20 μm larger than a thickness of the integrated circuit chip.

13. The packaged integrated circuit of claim 11 , wherein the depth of the cavity is about 5% to about 90% of a thickness of the integrated circuit chip.

14. The packaged integrated circuit of claim 13 , comprising a planarizing layer disposed on the structured glass article adjacent the integrated circuit chip.

15. The packaged integrated circuit of claim 11 , wherein the packaged integrated circuit is free of resin molding compound disposed within the cavity.

16. The packaged integrated circuit of claim 11 , wherein a difference between a first depth of the cavity at a first position along a perimeter of the cavity and a second depth of the cavity at a second position along the perimeter of the cavity opposite the first position is at most about 5 μm.

17. The packaged integrated circuit of claim 11 , comprising a redistribution layer disposed on the integrated circuit chip.

18. The packaged integrated circuit of claim 17 , comprising a ball grid array disposed on the redistribution layer.

19. The packaged integrated circuit of claim 11 , wherein:
the glass cladding layer comprises a first glass cladding layer fused to a first side of the glass base layer and a second glass cladding layer fused to a second side of the glass base layer opposite the first glass cladding layer;
the cavity comprises a first cavity formed in the first glass cladding layer and a second cavity formed in the second glass cladding layer; and
the integrated circuit chip comprises a first integrated circuit chip disposed within the first cavity and a second integrated circuit chip disposed within the second cavity.

20. The packaged integrated circuit of claim 19 , wherein the glass base layer is non-transmissive to radiation useful to expose at least one of the first glass cladding layer or the second glass cladding layer to form the cavity therein.

21. A wafer- or panel-level package comprising the packaged integrated circuit of claim 11 , wherein:
the cavity comprises a plurality of cavities, and
the integrated circuit chip comprises a plurality of integrated circuit chips each disposed within one of the plurality of cavities.

22. A method for making a reconstituted wafer- and/or panel-level package, the method comprising:
forming a plurality of cavities in a glass substrate comprising a glass cladding layer fused to a glass base layer, each cavity extending into the glass cladding layer from a surface thereof and having a depth; and
positioning an integrated circuit chip in each of the plurality of cavities in the glass substrate, the integrated circuit chip having a peripheral surface that faces one or more sidewalls of the cavity,
wherein a gap between the peripheral surface and the one or more sidewalls is no more than 20 μm in a direction normal to the depth.

Assignees

• Corning Inc

Inventors

• Boek Heather Debra
• Dohn Paul Bennett
• Kim Jin Su
• Li Aize
• Mcmahon Hugh Michael
• Yoon Jun-Ro

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/692

  Ceramics or glasses · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title