Busbar with tailored perforation sizes to provide thermal path

US11527357B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11527357-B2
Application numberUS-202117223366-A
CountryUS
Kind codeB2
Filing dateApr 6, 2021
Priority dateApr 10, 2020
Publication dateDec 13, 2022
Grant dateDec 13, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Disclosed is an assembly including a busbar that includes: a first layer that defines: first layer top and bottom surfaces; first layer first and second ends; and a first layer center region between the first layer first and second ends; and the first layer forms first layer perforations of different sizes about the first layer center region so perforations closer to the first layer first end are smaller than perforations spaced apart therefrom; a second layer that is disposed against and electrically isolated from the first layer bottom surface, wherein the second layer defines connector orifices having a same size as each other that are aligned with the first layer perforations; and a first capacitor supported against and electrically connected to the first layer top surface, wherein the first capacitor includes busbar connectors that respectively extend through the first layer perforations to electrically connect with the connector orifices.

First claim

Opening claim text (preview).

What is claimed is: 1. An assembly, comprising: a busbar that includes: a first layer, wherein: the first layer defines: a first layer top surface; a first layer bottom surface; a first layer first end; a first layer second end; and a first layer center region between the first layer first and second ends; and the first layer forms first layer perforations of different sizes about the first layer center region so that perforations closer to the first layer first end are smaller than perforations spaced apart from the first layer first end; a second layer, wherein the second layer is disposed against the first layer bottom surface and electrically isolated from the first layer, and wherein the second layer defines connector orifices, having a same size as each other, that are aligned with the first layer perforations; and a first capacitor, wherein the first capacitor is supported against and electrically connected to the first layer top surface, and wherein the first capacitor includes busbar connectors, and the busbar connectors respectively extend through the first layer perforations to electrically connect with the connector orifices. 2. The assembly of claim 1 , wherein: same sized perforations are positioned equidistant from the first layer first end. 3. The assembly of claim 2 , wherein: the first layer perforations are positioned along an arcuate axis. 4. The assembly of claim 3 , wherein: the first layer perforations are spaced apart from each other by a same or various pitch along the arcuate axis. 5. The assembly of claim 4 , wherein: the arcuate axis is a circumferential axis that defines a circle. 6. The assembly of claim 5 , wherein: a first perforation is closest to the first layer first end is smaller than each other of the first layer perforations. 7. The assembly of claim 6 , wherein: a second perforation is furthest from the first layer first end and is larger than each other of the first layer perforations. 8. The assembly of claim 7 , wherein: the first layer perforations include pairs of perforations between the first and second perforations. 9. The assembly of claim 8 , wherein the pairs of perforations include: a first pair of perforations that is closer to the first perforation than the second perforation; a second pair of perforations that is closer to the second perforation than the first perforation; a third pair of perforations that is intermediate the first and second pairs of perforations, and wherein: the first pair of perforations is smaller than the third pair of perforations; and the third pair of perforations is smaller than the second pair of perforations. 10. The assembly of claim 1 , wherein: the connector orifices are threaded holes; and the busbar connectors respectively connect to the connector orifices via bolts. 11. The assembly of claim 10 , further comprising: an insulation layer disposed against the first layer bottom surface, wherein the insulation layer forms insulation apertures that are respectively aligned with the first layer perforations. 12. The assembly of claim 1 , further comprising: a cooling plate connected to the first, second or third layer. 13. The assembly of claim 1 , wherein the busbar includes a third layer, wherein the first, second and third layers are electrically insulated from each other; and the assembly further includes a second capacitor, wherein the second capacitor is electrically connected to the second and third layers. 14. The assembly of claim 13 , wherein: the assembly is configured so that, in operation, the first layer is a positive busbar layer, the second layer is a neutral busbar layer and the third layer is a negative busbar layer. 15. A method of manufacturing an assembly, comprising: providing a first layer of a busbar that defines: a first layer top surface; a first layer bottom surface; a first layer first end; a first layer second end; a first layer center region between the first layer first and second ends; forming, about the first layer center region, first layer perforations of different sizes so that perforations closer to the first layer first end are smaller than perforations spaced apart from the first layer first end; positioning a second layer of the busbar against the first layer bottom surface so that the first and second layers are electrically isolated from each other, wherein the second layer defines connector orifices, having a same size as each other, that are aligned with the first layer perforations; supporting a first capacitor against the first layer top surface; and electrically connecting busbar connectors of the first capacitor with the connector orifices through the first layer perforations. 16. The method of claim 15 , wherein: forming the first layer perforations includes positioning the first layer perforations so that same sized perforations are equidistant from the first layer first end. 17. The method of claim 16 , wherein: forming the first layer perforations includes positioning the first layer perforations along an arcuate axis so that the first layer perforations are spaced apart from each other by a same or various pitch. 18. The method of claim 15 , further comprising: electrically connecting a second capacitor to the second layer and a third layer of the busbar so that the first, second and third layers are electrically isolated from each other. 19. The method of claim 18 , further comprising: configuring the first, second and third layers so that, in operation, the first layer is a positive busbar layer, the second layer is a neutral busbar layer and the third layer is a negative busbar layer.

Assignees

Inventors

Classifications

  • Terminals · CPC title

  • Multiple capacitors, i.e. structural combinations of fixed capacitors · CPC title

  • Housing; Encapsulation · CPC title

  • Housing; Encapsulation · CPC title

  • H02M7/003Primary

    Constructional details, e.g. physical layout, assembly, wiring or busbar connections · CPC title

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What does patent US11527357B2 cover?
Disclosed is an assembly including a busbar that includes: a first layer that defines: first layer top and bottom surfaces; first layer first and second ends; and a first layer center region between the first layer first and second ends; and the first layer forms first layer perforations of different sizes about the first layer center region so perforations closer to the first layer first end a…
Who is the assignee on this patent?
Hamilton Sundstrand Corp
What technology area does this patent fall under?
Primary CPC classification H02M7/003. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 13 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).