Display control system and related method of signal transmission

Patent metadata

Field	Value
Publication number	US-11527195-B2
Application number	US-202117238179-A
Country	US
Kind code	B2
Filing date	Apr 22, 2021
Priority date	Apr 22, 2021
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

A display control system includes a plurality of driver circuits connected in series. A driver circuit among the plurality of driver circuits includes a receiver, a duty cycle correction circuit and a transmitter. The receiver is configured to receive a first signal from a previous driver circuit among the plurality of driver circuits. The duty cycle correction circuit, coupled to the receiver, is configured to adjust a duty cycle of the first signal to generate a second signal. The transmitter, coupled to the duty cycle correction circuit, is configured to transmit the second signal to a next driver circuit among the plurality of driver circuits.

First claim

What is claimed is:

1. A display control system, comprising:
a plurality of driver circuits connected in series, among which a driver circuit comprises:
a receiver, configured to receive a first signal from a previous driver circuit among the plurality of driver circuits;
a duty cycle correction circuit, coupled to the receiver, configured to adjust a duty cycle of the first signal to generate a second signal; and
a transmitter, coupled to the duty cycle correction circuit, configured to transmit the second signal to a next driver circuit among the plurality of driver circuits.

2. The display control system of claim 1 , wherein each of the first signal and the second signal is a clock signal.

3. The display control system of claim 1 , wherein the plurality of driver circuits are configured to drive a light-emitting diode (LED) display panel.

4. The display control system of claim 1 , wherein the duty cycle correction circuit comprises:
a pulse generator, configured to generate a pulse signal according to the first signal;
a pulse interval detector, coupled to the pulse generator, configured to detect an interval length of two adjacent pulses in the pulse signal; and
an S-R latch, coupled to the pulse interval detector, configured to generate the second signal according to a detection result of the pulse interval detector.

5. The display control system of claim 4 , wherein the pulse generator comprises:
a delay cell, configured to generate a delay signal according to the first signal;
an inverter, coupled to the delay cell, configured to invert the delay signal or the first signal; and
an AND gate, coupled to the inverter, configured to generate the pulse signal according to the delay signal and the first signal.

6. The display control system of claim 4 , wherein the pulse interval detector comprises:
a first delay circuit, configured to generate a plurality of delay pulses according to the pulse signal;
a control logic, coupled to the first delay circuit, configured to determine a number of delay cells in the first delay circuit corresponding to the interval length of two adjacent pulses in the pulse signal according to the plurality of delay pulses; and
a second delay circuit, coupled to the control logic, configured to generate an output pulse with a delay time corresponding to one half of the interval length.

7. The display control system of claim 6 , wherein a number of delay cells included in the second delay circuit is one half of the number of delay cells included in the first delay circuit.

8. The display control system of claim 6 , wherein a delay time of the delay cells is adjustable.

9. The display control system of claim 1 , wherein the duty cycle correction circuit comprises:
a first filter;
an operator, coupled to the first filter;
an amplifier, comprising:
a first input terminal, coupled to the first filter;
a second input terminal; and
an output terminal, coupled to the operator.

10. The display control system of claim 9 , wherein the first filter is configured to filter the pulse signal to generate a filter signal, and the amplifier is configured to generate a feedback signal according to the filter signal and a reference voltage.

11. The display control system of claim 10 , wherein the operator is configured to generate the second signal according to the pulse signal and the feedback signal.

12. The display control system of claim 9 , wherein the duty cycle correction circuit further comprises:
a second filter, coupled to the second input terminal of the amplifier.

13. The display control system of claim 12 , wherein the second filter is configured to filter a reference clock to generate a reference voltage for the amplifier.

14. The display control system of claim 9 , wherein the duty cycle correction circuit further comprises:
a second filter, coupled to the second input terminal of the amplifier; and
a single-to-differential converter, coupled between the operator, the first filter and the second filter.

15. The display control system of claim 14 , wherein the single-to-differential converter is configured to convert the pulse signal into a first differential signal and a second differential signal, the first filter is configured to filter the first differential signal to generate a first filter signal, the second filter is configured to filter the second differential signal to generate a second filter signal, and the amplifier is configured to generate a feedback signal according to the first filter signal and the second filter signal.

16. The display control system of claim 9 , wherein the duty cycle correction circuit further comprises:
a second filter, coupled to the second input terminal of the amplifier; and
an inverter, coupled between the operator and the first filter.

17. The display control system of claim 16 , wherein the inverter is configured to invert the pulse signal to generate an inverse pulse signal, the first filter is configured to filter the inverse pulse signal to generate a first filter signal, the second filter is configured to filter the pulse signal to generate a second filter signal, and the amplifier is configured to generate a feedback signal according to the first filter signal and the second filter signal.

18. The display control system of claim 1 , wherein each of the first signal and the second signal is transmitted through at least one of a low voltage differential signaling (LVDS) interface and a mini-LVDS interface.

19. A method of signal transmission for a driver circuit among a plurality of driver circuits connected in series, the method comprising:
receiving a first signal from a previous driver circuit among the plurality of driver circuits;
adjusting a duty cycle of the first signal to generate a second signal; and
transmitting the second signal to a next driver circuit among the plurality of driver circuits.

20. The method of claim 19 , wherein each of the first signal and the second signal is a clock signal.

21. The method of claim 19 , wherein the plurality of driver circuits are configured to drive a light-emitting diode (LED) display panel.

22. The method of claim 19 , wherein each of the first signal and the second signal is transmitted through at least one of a low voltage differential signaling (LVDS) interface and a mini-LVDS interface.

Assignees

• Novatek Microelectronics Corp

Inventors

• Yeh Che-Wei
• Liang Keko-Chun
• Wang Yu-Hsiang
• Fang Yong-Ren
• Liu Yi-Chuan

Classifications

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• G09G5/18

  Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12}) · CPC title

• G09G2330/028

  Generation of voltages supplied to electrode drivers in a matrix display other than LCD · CPC title

• G09G3/3216 Primary

  using a passive matrix · CPC title

• G09G2370/14

  Use of low voltage differential signaling [LVDS] for display data communication · CPC title