Nonvolatile memory device performing a multiplication and accumulation operation

Patent metadata

Field	Value
Publication number	US-11526739-B2
Application number	US-202016838916-A
Country	US
Kind code	B2
Filing date	Apr 2, 2020
Priority date	Sep 5, 2019
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

A nonvolatile memory device includes a memory cell array and an computation output circuit. The memory cell array includes a plurality of nonvolatile memory elements configured to store a plurality of weights respectively and a plurality of bit lines coupled to the plurality of nonvolatile memory elements according to a plurality of input signals. The computation output circuit is configured to generate a computation signal from voltages induced at the plurality of bit lines according to the plurality of input signals.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a memory cell array including:
a plurality of nonvolatile memory elements configured to store a plurality of weights respectively, and
a plurality of bit lines coupled to the plurality of nonvolatile memory elements according to a plurality of input signals;

a computation output circuit configured to generate a computation signal from voltages respectively induced at the plurality of bit lines according to the plurality of input signals; and
an input circuit configured to convert the plurality of input signals into a plurality of pulse input signals,
wherein the memory cell array comprises:
a plurality of cell strings each including one of the plurality of nonvolatile memory elements, and
a plurality of bit line selection switches coupling the plurality of cell strings to the plurality of bit lines according to the plurality of input signals;

wherein the plurality of bit line selection switches couples the plurality of cell strings with the plurality of bit lines according to the plurality of pulse input signals; and
wherein the plurality of pulse input signals are pulse signals having widths respectively corresponding to respective values of the input signals.

2. The nonvolatile memory device of claim 1 ,
wherein the memory cell array further includes a plurality of word lines, and
wherein each of the plurality of cell strings includes a plurality of memory cells coupled in series, each memory cell in each cell string including a gate receiving a respective word line signal through a respective word line of the plurality of word lines.

3. The nonvolatile memory device of claim 1 , wherein the memory cell array further includes:
a source line, and
a plurality of source line selection switches coupling the plurality of cell strings to the source line according to a plurality of source line selection signals, respectively.

4. A nonvolatile memory device comprising:
a memory cell array including:
a plurality of nonvolatile memory elements configured to store a plurality of weights respectively, and
a plurality of bit lines coupled to the plurality of nonvolatile memory elements according to a plurality of input signals; and

a computation output circuit configured to generate a computation signal from voltages respectively induced at the plurality of bit lines according to the plurality of input signals,
wherein the computation output circuit includes a plurality of multiplication output circuits, and
wherein each of the plurality of multiplication output circuits generates a respective multiplication current corresponding to a product between a corresponding one of the plurality of input signals and a corresponding one of the plurality of weights.

5. The nonvolatile memory device of claim 4 , wherein a multiplication output circuit of the plurality of multiplication output circuits includes a current source configured to generate the multiplication current of the multiplication output circuit according to a voltage of a corresponding one among the plurality of bit lines.

6. The nonvolatile memory device of claim 5 , wherein the multiplication output circuit further includes:
a resistor coupling between a power source voltage and the corresponding one among the plurality of bit lines; and
a buffer configured to buffer a voltage of a common node between the resistor and the corresponding one among the plurality of bit lines in order to generate a buffer output voltage.

7. The nonvolatile memory device of claim 6 , wherein the current source is a p-channel Metal-Oxide-Semiconductor (PMOS) transistor including a gate receiving the buffer output voltage, a source coupled to the power source voltage, and a drain where the multiplication current of the multiplication output circuit is output.

8. The nonvolatile memory device of claim 7 , wherein the current source further comprises a resistor coupled between the power source voltage and the source of the PMOS transistor.

9. The nonvolatile memory device of claim 4 , wherein the computation output circuit further comprises an accumulation capacitor charged by the multiplication currents from the plurality of multiplication output circuits.

10. The nonvolatile memory device of claim 9 , wherein the computation output circuit further comprises a reset switch to discharge the accumulation capacitor according to a reset signal.

11. The nonvolatile memory device of claim 1 , wherein the nonvolatile memory device is a NAND flash memory device.

12. The nonvolatile memory device of claim 4 , wherein each of the plurality of weights is a K-bit data and each of the plurality of multiplication output circuits performs 2K−1 computation steps to generate the respective multiplication current, wherein K is a natural number, and wherein a read voltage provided to one of the plurality of nonvolatile memory elements is set different in each computation step.

Assignees

• Sk Hynix Inc
• Korea Advanced Institute Of Science And Tech Kaist

Inventors

• Seo Jin-O
• Lee Hyuk-Jin
• Cho Seonghwan

Classifications

• G06N3/065

  Analogue means · CPC title

• G06N3/045

  Combinations of networks · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G06F7/523

  Multiplying only · CPC title