Analog processor comprising quantum devices

Patent metadata

Field	Value
Publication number	US-11526463-B2
Application number	US-202117355458-A
Country	US
Kind code	B2
Filing date	Jun 23, 2021
Priority date	Dec 23, 2004
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

First claim

We claim:

1. A quantum processor, comprising:
a plurality of quantum devices; and
a plurality of coupling devices wherein each coupling device in the plurality of coupling devices couples a pair of quantum device wherein a non-planar graph is embedded into the plurality of quantum devices and a set of quantum devices in the plurality of quantum devices are nodes of the non-planar graph.

2. The quantum processor of claim 1 wherein a quantum device in the plurality of quantum devices comprises a loop of superconducting material interrupted by at least one Josephson junction.

3. The quantum processor of claim 2 wherein at least one of the Josephson junctions in the quantum device is a compound Josephson junction.

4. The quantum processor of claim 1 wherein the plurality of quantum devices is arranged in a two-dimensional array, wherein the two-dimensional array has a width defined by a first plurality of nodes n, and a length defined by a second plurality of nodes m, and wherein the two-dimensional array comprises an interior and a perimeter.

5. The quantum processor of claim 1 wherein a quantum device in the plurality of quantum devices has a gradiometric configuration.

6. The quantum processor of claim 1 wherein at least one coupling device in the plurality of coupling devices comprises a loop of superconducting material interrupted by at least one Josephson junction.

7. The quantum processor of claim 1 wherein at least one coupling device in the plurality of coupling devices comprises a loop of superconducting material interrupted by at least one compound Josephson junction.

8. The quantum processor of claim 1 wherein at least one coupling device in the plurality of coupling devices is selected from the group consisting of an rf-SQUID and a dc-SQUID.

9. The quantum processor of claim 1 , further comprising:
a readout device that is configured to readout a state of at least one quantum device in the plurality of quantum devices.

10. The quantum processor of claim 9 wherein the readout device is selected from the group consisting of a dc-SQUID and a magnetometer.

11. The quantum processor of claim 1 wherein the plurality of quantum devices is arranged in a lattice.

12. A computer system for determining a result of a computational problem, the computer system comprising:
a central processing unit; and
a non-transitory computer-readable storage medium coupled to the central processing unit and which stores instructions that cause the computer system to:
present a user interface that enables a user to provide a definition of a computational problem;
receive the definition of the computational problem;
generate a mapping of the computational problem;
transmit the mapping to an analog processor, the analog processor comprising a plurality of quantum devices and a plurality of coupling devices, the mapping including initialization values for at least one of the quantum devices in the plurality of quantum devices and initialization values for at least one of the coupling devices in the plurality of coupling devices, wherein a coupling device in the plurality of coupling devices couples a corresponding respective quantum device in the plurality of quantum devices to at least one of a nearest neighbor of the respective quantum device and a next-nearest neighbor of the respective quantum device; and
receive a result, responsive to the mapping, from the analog processor.

13. The computer system of claim 12 , wherein the computational problem is selected from the group consisting of a problem having a complexity of P, a problem having a complexity of NP, a problem having a complexity of NP-Hard and a problem having a complexity of NP-Complete.

14. The computer system of claim 12 , wherein the computational problem is selected from the group consisting of an Ising Spin Glass problem, a Maximum Independent Set problem, a Max Clique problem, a Max Cut problem, a traveling salesperson problem, a k-SAT problem and an integer linear programming problem.

15. The computer system of claim 12 , wherein the user interface enables the user to define at least one run-time control parameter.

16. The computer system of claim 12 , wherein the instructions to generate a mapping of the computational problem comprise instructions to map an NP problem into an equivalent representation in an Ising model.

17. The computer system of claim 12 , wherein the user provided definition of the computational problem comprises an input graph representation of the computational problem and wherein the instructions to generate a mapping of the computational problem cause the computer system to map the computational problem from the input graph representation to an equivalent graph representation that maps to a configuration of the analog processor.

18. A method of determining a result for a computational problem using a quantum processor, the quantum processor comprising at least two quantum devices and at least one coupling device and each coupling device couples a pair of quantum devices, the method comprising:
initializing the quantum processor to an initial state, wherein each quantum device in the quantum processor is a node in a lattice of nodes;
mapping a graph representing the computational problem onto at least a portion of the lattice of nodes;
evolving the quantum processor after mapping the graph onto at least a portion of the lattice;
determining a value of at least one node in the lattice of nodes after evolving the quantum processor; and
generating a carrier wave embodying a data signal comprising a result for the computational problem, wherein result for the computational problem comprises the value of the at least one node in the lattice of nodes.

19. The method of claim 18 , further comprising configuring the graph of the computational problem to be solved so that it can be mapped to the lattice of the quantum processor, the graph of the computational problem to be solved comprising a plurality of nodes and, for each respective node in the plurality of nodes, an initial value for the respective node and a corresponding coupling constant between the respective node and another node in the plurality of nodes.

20. The method of claim 18 , further comprising converting the computational problem to be solved to a graph comprising a plurality of nodes prior to mapping the graph onto the at least a portion of the lattice of nodes of the quantum processor, the converted problem comprising, for each respective node in the plurality of nodes, an initial value for the respective node and a corresponding coupling constant between the respective node and another node in the plurality of nodes.

Assignees

• D Wave Systems Inc

Inventors

• Maassen Van Den Brink Alexander
• Love Peter
• Amin Mohammad H S
• Rose Geordie
• Grant David
• Steininger Miles F H
• Bunyk Paul I
• Berkley Andrew J

Classifications

• H03K3/38

  by the use, as active elements, of superconductive devices · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• G06G7/12

  Arrangements for performing computing operations, e.g. {operational} amplifiers specially adapted therefor · CPC title

• G06J3/00 Primary

  Systems for conjoint operation of complete digital and complete analogue computers · CPC title

• G06F15/80 Primary

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title