Limited propagation of unnecessary memory updates

Patent metadata

Field	Value
Publication number	US-11526449-B2
Application number	US-202017007133-A
Country	US
Kind code	B2
Filing date	Aug 31, 2020
Priority date	Aug 31, 2020
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

A processing system limits the propagation of unnecessary memory updates by bypassing writing back dirty cache lines to other levels of a memory hierarchy in response to receiving an indication from software executing at a processor of the processing system that the value of the dirty cache line is dead (i.e., will not be read again or will not be read until after it has been overwritten). In response to receiving an indication from software that data is dead, a cache controller prevents propagation of the dead data to other levels of memory in response to eviction of the dead data or flushing of the cache at which the dead data is stored.

First claim

What is claimed is:

1. A method comprising:
in response to evicting a dirty cache line from a first cache of a processor, bypassing writing the dirty cache line to a second cache or memory of the processor in response to receiving an indication that the dirty cache line is dead.

2. The method of claim 1 , wherein the indication is received from software executing at the processor and comprises a dead data operation indicating that a value of the dirty cache line of the first cache will not be read again or will be subsequently overwritten before being read again.

3. The method of claim 1 , further comprising:
tracking, at a buffer, address ranges corresponding to dirty cache lines that will not be subsequently read or that will be overwritten before being subsequently read.

4. The method of claim 3 , further comprising:
comparing an address corresponding to the dirty cache line to the address ranges tracked at the buffer; and
bypassing writing the dirty cache line to the second cache or memory in response to the address corresponding to the dirty cache line being included in the address ranges.

5. The method of claim 3 , further comprising:
clearing a dirty bit associated with an address range corresponding to a dirty cache line that will not be subsequently read.

6. The method of claim 3 , further comprising:
querying the buffer prior to copying a page of data to a new physical location; and
bypassing copying a portion of the page of data to the new physical location in response to determining that the portion includes an address tracked at the buffer.

7. A method comprising:
receiving, at a cache controller for a first cache of a processor, the first cache storing a plurality of dirty cache lines, an indication that a subset of the dirty cache lines are dead; and
in response to a flush operation or eviction of a dirty cache line from the first cache, selectively writing back only the dirty cache lines not included in the subset of the dirty cache lines to a second cache.

8. The method of claim 7 , wherein the indication comprises a dead data operation indicating that values of the subset of the dirty cache lines will not be subsequently read or will be overwritten before being subsequently read.

9. The method of claim 8 , further comprising:
tracking, at a buffer, address ranges corresponding to dirty cache lines that will not be subsequently read or that will be overwritten before being subsequently read.

10. The method of claim 9 , further comprising:
comparing an address corresponding to a dirty cache line to the address ranges tracked at the buffer; and
bypassing writing the dirty cache line to the second cache in response to the address corresponding to the dirty cache line being included in the address ranges.

11. The method of claim 9 , further comprising:
clearing a dirty bit associated with an address range corresponding to a dirty cache line that will not be subsequently read.

12. The method of claim 9 , further comprising:
querying the buffer prior to copying a page of data to a new physical location; and
bypassing copying a portion of the page of data to the new physical location in response to determining that the portion includes an address tracked at the buffer.

13. A processor comprising:
a first cache configured to store dirty cache lines;
a second cache; and
a cache controller associated with the first cache, the cache controller to:
receive an indication that a dirty cache line is dead; and
in response to a flush operation or eviction of dirty cache lines from the first cache, bypass writing back the dirty cache line to the second cache based on the indication.

14. The processor of claim 13 , wherein the indication comprises a dead data operation indicating that a value of the dirty cache line will not be subsequently read or will be overwritten before being subsequently read.

15. The processor of claim 13 , wherein the cache controller is further to:
in response to a new store operation for the dirty cache line, indicate the dirty cache line is no longer dead.

16. The processor of claim 13 , further comprising:
a buffer, wherein the cache controller is further to:
track, at the buffer, address ranges corresponding to dirty cache lines that will not be subsequently read or will be overwritten before they are subsequently read.

17. The processor of claim 16 , wherein the cache controller is further to:
compare an address corresponding to the dirty cache line to the address ranges tracked at the buffer; and
bypass writing the dirty cache line to the second cache in response to the address corresponding to the dirty cache line being included in the address ranges.

18. The processor of claim 16 , wherein the cache controller is further to:
modify the address ranges to remove a tracked address in response to receiving a store operation indicating that data stored at the tracked address has been overwritten.

19. The processor of claim 16 , further comprising:
an operating system to:
query the buffer prior to copying a page of data to a new physical location; and
bypass copying a portion of the page of data to the new physical location in response to determining that the portion includes an address tracked at the buffer.

20. The processor of claim 13 , wherein the cache controller is further to:
clear a dirty bit associated with an address range corresponding to a dirty cache line that is dead.

Assignees

• Advanced Micro Devices Inc

Inventors

• Alsop Johnathan
• Fotouhi Pouya
• Beckmann Bradford
• Blagodurov Sergey

Classifications

• G06F12/0882

  Page mode · CPC title

• G06F12/0891 Primary

  using clearing, invalidating or resetting means · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F9/30047

  Prefetch instructions; cache control instructions · CPC title