Methods and apparatus to implement always-on context sensor hubs for processing multiple different types of data inputs

Patent metadata

Field	Value
Publication number	US-11526205-B2
Application number	US-201815734820-A
Country	US
Kind code	B2
Filing date	Dec 31, 2018
Priority date	Dec 31, 2018
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

Methods and apparatus to implement always-on context sensor hubs for processing multiple different types of data inputs are disclosed. An examples apparatus includes a first processor core to implement a host controller, and a second processor core to implement an offload engine. The host controller includes first logic to process sensor data associated with an electronic device when the electronic device is in a low power mode. The host controller is to offload a computational task associated with the sensor data to the offload engine. The offload engine includes second logic to execute the computational task.

First claim

What is claimed is:

1. An apparatus comprising:
a first processor core to implement a host controller, the first processor core to consume a first amount of power within a first power range associated with a first power domain;
a second processor core to implement an offload engine, the second processor core to consume a second amount of power within the first power range associated with the first power domain, the host controller including first logic to process sensor data associated with an electronic device, the first and second processor cores to operate in the first power domain, the first power domain to enable the electronic device to be in a low power mode while at least one of the first processor core or the second processor core is in operation, the host controller to offload a computational task associated with the sensor data to the offload engine, the offload engine including second logic to execute the computational task; and
a third processor core to operate in a second power domain and to consume a third amount of power within a second power range associated with the second power domain, the second power range lower than the first power range, the second power domain associated with more power than an off state, the third amount of power less than the first amount of power and less than the second amount of power.

2. The apparatus as defined in claim 1 , wherein the third processor core is to monitor a sensor associated with the electronic device when the first and second processor cores are asleep.

3. The apparatus as defined in claim 2 , wherein the third processor core is to detect a trigger event based on sensor data output by the sensor and to wake up the host controller in response to the trigger event.

4. The apparatus as defined in claim 2 , wherein the host controller includes a hardware driver for the sensor.

5. The apparatus as defined in claim 1 , wherein the host controller includes a wrapper associated with the second logic.

6. The apparatus as defined in claim 1 , wherein the offload engine is a first offload engine, the apparatus further including a fourth processor core to implement a second offload engine, the first offload engine to implement first sensor data analysis and the second offload engine to implement second sensor data analysis, the first sensor data analysis different than the second sensor data analysis.

7. The apparatus as defined in claim 6 , wherein the first sensor data analysis corresponds to a vision detection analysis and the second sensor data analysis corresponds to a vision recognition analysis.

8. The apparatus as defined in claim 6 , wherein the first sensor data analysis corresponds to at least one of a vision detection analysis or a vision recognition analysis and the second sensor data analysis corresponds to at least one of a speech detection analysis or a voice recognition analysis.

9. The apparatus as defined in claim 8 , wherein the second processor core includes a convolution neural network accelerator and the third processor core includes a deep neural network accelerator.

10. The apparatus as defined in claim 8 , wherein the host controller is to include third logic to determine a location of the electronic device.

11. The apparatus as defined in claim 1 , wherein the host controller and the offload engine are to communicate via interprocess communication.

12. The apparatus as defined in claim 11 , wherein the host controller is to offload the computational task by calling an application programming interface (API) proxy associated with the interprocess communication.

13. The apparatus as defined in claim 1 , wherein the host controller includes a runtime environment to execute a user loaded application when the electronic device is in the low power mode.

14. The apparatus as defined in claim 1 , further including memory shared by the first and second processor cores, the memory having a first memory size, the host controller to communicate with an application processor of the electronic device to load a block of data, the block of data associated with a second memory size larger than the first memory size.

15. An apparatus comprising:
a first processor core to implement a host controller; and
a second processor core to implement an offload engine, the host controller including first logic to process sensor data associated with an electronic device when the electronic device is in a low power mode, the host controller to offload a computational task associated with the sensor data to the offload engine, the offload engine including second logic to execute the computational task, the host controller to maintain a data structure defining client-server relationships between different sensor data sources, the different sensor data sources corresponding to either a sensor hardware driver or sensor data processing logic, the data structure to identify which one of the first processor core or the second processor core is to include respective ones of the sensor data sources, the first processor core and the second processor core to operate in a first power domain, the first power domain associated with an operating power between 1 mW and 20 mW.

16. The apparatus as defined in claim 15 , wherein the host controller is to determine when none of the sensor data sources of the host controller are running, and to put the host controller to sleep based on the determination.

17. An apparatus comprising:
a first processor core to implement a host controller;
a second processor core to implement a first offload engine, the host controller including first logic to process sensor data associated with an electronic device when the electronic device is in a low power mode, the host controller to offload a computational task associated with the sensor data to the first offload engine, the first offload engine including second logic to execute the computational task, the host controller to maintain a data structure defining client-server relationships between different sensor data sources, the different sensor data sources corresponding to either a sensor hardware driver or sensor data processing logic, the data structure to identify which one of the first processor core or the second processor core is to include respective ones of the sensor data sources; and
a third processor core to implement a second offload engine, the host controller to share the data structure with the first and second offload engines, at least one of the host controller, the first offload engine, or the second offload engine to determine whether to wake up a different one of the at least one of the host controller, the first offload engine, or the second offload engine based on the client-server relationships between the different sensor data sources.

18. A non-transitory computer readable medium comprising instructions that, when executed, cause at least one system to at least:
process, with first logic of a first processor core that consumes a first amount of power when in operation, sensor data associated with an electronic device while the electronic device is in a sleep mode, the sensor data generated while the electronic device is in the sleep mode, the first amount of power within a first power range associated with a first power domain;
offload a computational task associated with the sensor data to an offload engine implemented in a second processor core that consumes a second amount of power when in operation, the second amount of power within the first power range associated with the first power domain;
process, based on second lo

Assignees

• Intel Corp

Inventors

• Han Ke
• Sun Mingqiu
• Wang Dong
• Iyer Prakash
• Jourdan Stephan
• Mialkowski Andrzej

Classifications

• G06N3/063 Primary

  using electronic means · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06N5/04

  Inference or reasoning models · CPC title

• G06F1/3215 Primary

  Monitoring of peripheral devices · CPC title

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title