Dynamic latch based SPAD front end

Patent metadata

Field	Value
Publication number	US-11525904-B2
Application number	US-201916661119-A
Country	US
Kind code	B2
Filing date	Oct 23, 2019
Priority date	Oct 23, 2019
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

A time-of-flight ranging system disclosed herein includes a receiver asserting a photon received signal in response to detection of light that has reflected off a target and returned to the time-of-flight ranging system. A first latch circuit has first and second data inputs receiving a first pair of differential timing references, the first latch circuit latching data values at its first and second data inputs to first and second data outputs based upon assertion of the photon received signal. A first counter counts latching events of the first latch circuit during which the first data output is asserted, and a second counter counts latching events of the first latch circuit during which the second data output is asserted. Processing circuitry determines distance to the target based upon counted latching events output from the first and second counters.

First claim

The invention claimed is:

1. A time of flight ranging system, comprising:
a receiver configured to assert a photon received signal in response to detection of light that has reflected off a target and returned to the time of flight ranging system; and
a first latch circuit having first and second data inputs receiving a first pair of differential timing references, the first latch circuit being configured to latch data values at its first and second data inputs based upon assertion of the photon received signal.

2. The time of flight ranging system of claim 1 , wherein the first latch circuit latches data values at its first data input to a first data output; and further comprising:
a first counter configured to count latching events of the first latch circuit during which the first data output is asserted; and
a second counter configured to count latching events of the first latch circuit during which an inversion of a voltage at the first data output is asserted.

3. The time of flight ranging system of claim 1 , wherein the first latch circuit latches data values at its first and second data inputs to first and second data outputs; and further comprising:
a first counter configured to count latching events of the first latch circuit during which the first data output is asserted; and
a second counter configured to count latching events of the first latch circuit during which the second data output is asserted.

4. The time of flight ranging system of claim 1 ,
further comprising a control signal generation block configured to generate a latch command signal by applying a delay to the photon received signal;
wherein the first latch circuit has an enable input receiving the latch command signal; and
wherein the first latch circuit is configured to latch in response to assertion of the latch command signal.

5. The time of flight ranging system of claim 4 , wherein the first latch circuit latches data values at its first data input to a first data output;
wherein the control signal generation block is further configured to:
generate a delayed latch command signal by applying a delay to the latch command signal; and
generate a toggle control signal by performing a logical operation on the delayed latch command signal and the photon received signal;

further comprising a first AND gate performing a logical AND on the first data output and the toggle control signal to produce a toggle signal;
further comprising a first ripple counter having a clock input receiving the toggle signal;
further comprising a second AND gate performing a logical AND operation on an inverted version of the first data output and the toggle control signal to produce a complement of the toggle signal; and
further comprising a second ripple counter having a clock input receiving the complement of the toggle signal.

6. The time of flight ranging system of claim 5 , wherein the logical operation performed by the control signal generation block on the delayed latch command signal and the photon received signal to generate the toggle control signal is a logical AND operation.

7. The time of flight ranging system of claim 5 ,
wherein the control signal generation block is further configured to generate a complement of the latch command signal by applying a delay to a complement of the photon received signal; and
wherein the first latch circuit comprises:
a first transmission gate having an input coupled to the first data input and an output coupled to the first data output, the first transmission gate configured to open in response to deassertion of the latch command signal and assertion of the complement of the latch command signal; and
a second transmission gate having an input coupled to the second data input, the second transmission gate configured to open in response to deassertion of the latch command signal and assertion of the latch command signal.

8. The time of flight ranging system of claim 7 ,
wherein the first latch circuit further comprises:
first and second CMOS inverters in a cross coupled arrangement, with an input of the first CMOS inverter coupled to an output of the second CMOS inverter and with an input of the second CMOS inverter coupled to an output of the first CMOS inverter;
a first enable circuit configured to control coupling of a supply voltage to supply terminals of the first and second CMOS inverters in response to deassertion of the complement of the latch command signal; and
a second enable circuit configured to control coupling of a ground voltage to ground terminals of the first and second CMOS inverters in response to assertion of the latch command signal;

wherein the output of the first CMOS inverter is the first data output of the first latch circuit.

9. The time of flight ranging system of claim 4 ,
wherein the first latch circuit latches data values at its first and second data inputs to first and second data outputs;
wherein the control signal generation block is further configured to:
generate a delayed latch command signal by applying a delay to the latch command signal; and
generate a toggle control signal by performing a logical operation on the delayed latch command signal and the photon received signal;

further comprising a first AND gate performing a logical AND on the first data output and the toggle control signal to produce a toggle signal;
further comprising a first ripple counter having a clock input receiving the toggle signal;
further comprising a second AND gate performing a logical AND operation on the second data output and the toggle control signal to produce a complement of the toggle signal; and
further comprising a second ripple counter having a clock input receiving the complement of the toggle signal.

10. The time of flight ranging system of claim 9 , wherein the logical operation performed by the control signal generation block on the delayed latch command signal and the photon received signal to generate the toggle control signal is a logical AND operation.

11. The time of flight ranging system of claim 9 ,
wherein the control signal generation block is further configured to generate a complement of the latch command signal by applying a delay to a complement of the photon received signal; and
wherein the first latch circuit comprises:
a first transmission gate having an input coupled to the first data input and an output coupled to the first data output, the first transmission gate configured to open in response to deassertion of the latch command signal and assertion of the complement of the latch command signal; and
a second transmission gate having an input coupled to the second data input and an output coupled to the second data output, the second transmission gate configured to open in response to deassertion of the latch command signal and assertion of the latch command signal.

12. The time of flight ranging system of claim 11 ,
wherein the first latch circuit further comprises:
first and second CMOS inverters in a cross coupled arrangement, with an input of the first CMOS inverter coupled to an output of the second CMOS inverter and with an input of the second CMOS inverter coupled to an output of the first CMOS inverter;
a first enable circuit configured to control coupling of a supply voltage to supply terminals of the first and second CMOS inverters in response to deassertion of the complement of the latch command signal; and
a second enable circuit configured to control coupling of a ground voltage to ground terminals of the first and second CMOS inverters in response to assertion of the latch command signal;

wherein the output of the first CMOS inverter is the first data out

Assignees

• St Microelectronics Res & Dev Ltd

Inventors

• Moore John Kevin
• Dutton Neale

Classifications

• G01S7/4914 Primary

  of detector arrays, e.g. charge-transfer gates · CPC title

• G01S7/4808

  Evaluating distance, position or velocity data · CPC title

• G01S7/4913 Primary

  Circuits for detection, sampling, integration or read-out · CPC title

• G01S17/32

  using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated · CPC title

• G01S7/4915

  Time delay measurement, e.g. operational details for pixel components (signal extraction and conditioning G01S7/493); Phase measurement · CPC title