Packed error correction code (ECC) for compressed data protection

Patent metadata

Field	Value
Publication number	US-11522565-B2
Application number	US-202117224434-A
Country	US
Kind code	B2
Filing date	Apr 7, 2021
Priority date	Apr 7, 2021
Publication date	Dec 6, 2022
Grant date	Dec 6, 2022

Abstract

A packed error correction code (ECC) technique opportunistically embeds ECC check-bits with compressed data. When compressed, the data is encoded in fewer bits and is therefore fragmented when stored or transmitted compared with the uncompressed data. The ECC check-bits may be packed with compressed data at “source” points. The check-bits are transmitted along with the compressed data and, at any “intermediate” point between the source and a “destination” the check-bits may be used to detect and correct errors in the compressed data. In contrast with conventional systems, packed ECC enables end-to-end coverage for sufficiently-compressed data within the processor and also externally. While storage circuitry typically is protected by structure-specific ECC, protection is also beneficial for data as it is transmitted between processing and/or storage units.

First claim

What is claimed is:

1. A computer-implemented method, comprising:
processing compressed data within a processor to compute error correction code check-bits;
determining a number of fixed size storage units needed to store a combination of the compressed data and check-bits;
combining the compressed data and the check-bits into the number of fixed size storage units to produce a combination; and
transmitting the combination within the processor or to an additional device that is external to the processor.

2. The computer-implemented method of claim 1 , further comprising
determining that the number exceeds a maximum number of the fixed size storage units;
removing the check-bits from the combination; and
separately transferring the check-bits within the processor or to the additional device.

3. The computer-implemented method of claim 1 , further comprising discarding the check-bits at an interface with the additional device and transmitting only the compressed data from the processor to the additional device.

4. The computer-implemented method of claim 1 , further comprising storing the combination in a memory device at a location accessed by an address that is read or written using a single access request.

5. The computer-implemented method of claim 1 , further comprising storing the compressed data in a first portion of a memory device and storing the check-bits in a second portion of the memory device that is separate from the first portion.

6. The computer-implemented method of claim 1 , wherein the combination is transmitted from the processor to the additional device over an interconnect.

7. The computer-implemented method of claim 1 , wherein the combination is transmitted through a crossbar interconnect within the processor.

8. The computer-implemented method of claim 1 , wherein a second number of the fixed size storage units is needed to store the compressed data without the check-bits and the second number is less than the number of the fixed size storage units needed to store the combination.

9. The computer-implemented method of claim 1 , wherein the error correction code check-bits are separately computed for a portion of the compressed data in each fixed size storage unit and combined in the fixed size storage unit with the portion of the compressed data.

10. A computer-implemented method of claim 1 , wherein the combination is transmitted to a storage resource within the processor and further comprising:
determining, based on the check-bits whether the compressed data is corrupted; and
storing the combination in the storage resource, wherein, responsive to determining that the compressed data is corrupted, correcting the compressed data using the check-bits before storing the combination.

11. The computer-implemented method of claim 10 , wherein the combination is transmitted to the storage resource through a crossbar interconnect within the processor.

12. The computer-implemented method of claim 10 , further comprising:
receiving, by an execution core within the processor, the combination from the storage resource;
determining, by the execution core that the compressed data is corrupted based on the check-bits; and
correcting the compressed data using the check-bits before processing the compressed data by the execution core.

13. The computer-implemented method of claim 1 , further comprising:
determining, by the additional device that the compressed data is corrupted; and
correcting the compressed data using the check-bits before processing the combination within the additional device.

14. The computer-implemented method of claim 1 , wherein at least one of the steps of processing, determining, and combining are performed on a server or in a data center to generate an image, and the image is streamed to a user device.

15. The computer-implemented method of claim 1 , wherein at least one of the steps of processing, determining, and combining are performed within a cloud computing environment.

16. The computer-implemented method of claim 1 , wherein at least one of the steps of processing, determining, and combining are performed for training, testing, or certifying a neural network employed in a machine, robot, or autonomous vehicle.

17. The computer-implemented method of claim 1 , wherein at least one of the steps of processing, determining, and combining is performed on a virtual machine comprising a portion of a graphics processing unit.

18. A system, comprising:
a processor comprising an interface; and
an additional device that is external to the processor and connected to the interface, wherein the processor is configured to protect compressed data by:
processing the compressed data to compute error correction code check-bits;
determining a number of fixed size storage units needed to store a combination of the compressed data and check-bits; and
combining the compressed data and the check-bits into the number of fixed size storage units for transfer within the processor or to the additional device that is external to the processor.

19. The system of claim 18 , further comprising transmitting the combination through a crossbar interconnect within the processor.

20. A non-transitory computer-readable media storing computer instructions that, when executed by one or more processors, cause the one or more processors to perform the steps of:
processing compressed data to compute error correction code check-bits;
determining a number of fixed size storage units needed to store a combination of the compressed data and check-bits; and
combining the compressed data and the check-bits into the number of fixed size storage units for transfer within a first processor of the one or more processors or to an additional device that is external to the first processor.

Assignees

• Nvidia Corp

Inventors

• Sullivan Michael Brendan
• Pool Jeffrey Michael
• Huang Yangxiang
• Tsai Timothy Kohchih
• Hari Siva Kumar Sastry
• Keckler Steven William

Classifications

• G06F11/1044 Primary

  with specific ECC/EDC distribution · CPC title

• H03M13/6312 Primary

  Error control coding in combination with data compression · CPC title

• G06F11/1076

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• G06F13/4027 Primary

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06N3/04

  Architecture, e.g. interconnection topology · CPC title