Active common mode compensation for improved amplifier performance

Patent metadata

Field	Value
Publication number	US-11522507-B2
Application number	US-202117213084-A
Country	US
Kind code	B2
Filing date	Mar 25, 2021
Priority date	Mar 25, 2021
Publication date	Dec 6, 2022
Grant date	Dec 6, 2022

Abstract

Various techniques are provided to reduce common mode disturbance associated with an amplifier, such as a class D amplifier. In one example, an amplifier includes a power stage configured to generate first and second PWM signals. The amplifier further includes an integration stage comprising input nodes configured to receive an input differential analog signal. The integration stage is configured to generate an output differential analog signal in response to the PWM signals and the input differential analog signal. The amplifier further includes an active compensation circuit configured to provide a compensation signal to the integration stage to reduce disturbances at the input nodes associated with the PWM signals switching between a common mode and a differential mode. Additional devices, systems, and methods are also provided.

First claim

What is claimed is:

1. An amplifier comprising:
a power stage configured to generate first and second PWM signals;
an integration stage comprising input nodes configured to receive an input differential analog signal, wherein the integration stage is configured to generate an output differential analog signal in response to the PWM signals and the input differential analog signal; and
an active compensation circuit configured to provide a compensation signal to the integration stage to reduce disturbances at the input nodes associated with the PWM signals switching between a common mode and a differential mode, the compensation signal having:
a low voltage responsive to the PWM signals being in a first common mode configuration;
a high voltage responsive to the PWM signals being in a second common mode configuration; and
an intermediate voltage responsive to the PWM signals being in a differential mode configuration.

2. The amplifier of claim 1 , wherein the compensation circuit comprises logic circuits configured to generate the compensation signal synchronously with the PWM signals.

3. The amplifier of claim 2 , wherein the logic circuits are configured to receive the PWM signals and generate the compensation signal in response thereto.

4. The amplifier of claim 1 , wherein:
the integration stage and the compensation circuit are implemented in a loop filter of the amplifier; and
the loop filter further comprises a differential analog current source configured to provide the input differential analog signal.

5. The amplifier of claim 4 , wherein the integration stage is configured to generate the output differential analog signal in response to voltages generated at the input nodes by a current flow of the input differential analog signal in response to voltage transitions of the PWM signals.

6. The amplifier of claim 1 , wherein:
the integration stage is a first integration stage; and
the amplifier further comprises second and third integration stages in series with the first integration stage and configured to receive the compensation signal.

7. The amplifier of claim 1 , wherein the integration stage further comprises a capacitor of 5 pf or less configured to provide a low pass filter to further reduce the disturbances.

8. The amplifier of claim 1 , wherein the amplifier is a class D amplifier.

9. The amplifier of claim 1 , wherein the amplifier is implemented in a wireless headset system.

10. A method comprising:
providing, by a power stage of an amplifier, first and second PWM signals to an integration stage of the amplifier;
receiving, at input nodes of the integration stage, an input differential analog signal;
generating, by the integration stage, an output differential analog signal in response to the PWM signals and the input differential analog signal; and
providing, by an active compensation circuit of the amplifier, a compensation signal to the integration stage to reduce disturbances at the input nodes associated with the PWM signals switching between a common mode and a differential mode, the compensation signal having:
a low voltage responsive to the PWM signals being in a first common mode configuration;
a high voltage responsive to the PWM signals being in a second common mode configuration; and
an intermediate voltage responsive to the PWM signals being in a differential mode configuration.

11. The method of claim 10 , further comprising generating the compensation signal by logic circuits of the compensation circuit synchronously with the PWM signals.

12. The method of claim 11 , further comprising:
receiving the PWM signals by the logic circuits; and
wherein the logic circuits generate the compensation circuit in response to the PWM signals.

13. The method of claim 10 , wherein:
the integration stage and the compensation circuit are implemented in a loop filter of the amplifier; and
the method further comprises providing the input differential analog signal by a differential analog current source of the loop filter.

14. The method of claim 13 , wherein the generating the output differential analog signal is performed in response to voltages generated at the input nodes by a current flow of the input differential analog signal in response to voltage transitions of the PWM signals.

15. The method of claim 10 , wherein:
the integration stage is a first integration stage; and
the amplifier further comprises second and third integration stages in series with the first integration stage and configured to receive the compensation signal.

16. The method of claim 10 , wherein the integration stage further comprises a capacitor of 5 pf or less configured to provide a low pass filter to further reduce the disturbances.

17. The method of claim 10 , wherein the amplifier is a class D amplifier.

18. The method of claim 10 , wherein the amplifier is implemented in a wireless headset system.

Assignees

• Synaptics Inc

Inventors

• Shen Dan
• Lan Jinbao
• Zhang Yunfu
• Crespi Lorenzo

Classifications

• H03F2200/372

  Noise reduction and elimination in amplifier · CPC title

• H03F3/217 Primary

  Class D power amplifiers; Switching amplifiers · CPC title

• H03F1/26 Primary

  Modifications of amplifiers to reduce influence of noise generated by amplifying elements · CPC title

• H03F2200/351

  Pulse width modulation being used in an amplifying circuit · CPC title

• H03F2200/129

  there being a feedback over the complete amplifier · CPC title