Memory device and method of operating the same

Patent metadata

Field	Value
Publication number	US-11521684-B2
Application number	US-202117308583-A
Country	US
Kind code	B2
Filing date	May 5, 2021
Priority date	Dec 2, 2020
Publication date	Dec 6, 2022
Grant date	Dec 6, 2022

Abstract

A memory device, and a method of operating the same, includes a memory cell array coupled to a plurality of word lines, wherein each word line is coupled to a plurality of memory cells. The memory device also includes a peripheral circuit configured to perform a sensing operation of sensing selected memory cells coupled to a selected word line selected from among the plurality of word lines. The memory device further includes control logic configured to control the peripheral circuit apply a turn-on voltage to a block word line coupled to the selected word line when the sensing operation is terminated and when potentials of the plurality of word lines are increased due to a recovery operation for channels of the plurality of memory cells after the plurality of word lines have been discharged.

First claim

What is claimed is:

1. A memory device, comprising:
a memory cell array coupled to a plurality of word lines, wherein each word line is coupled to a plurality of memory cells;
a peripheral circuit configured to perform a sensing operation of sensing selected memory cells coupled to a selected word line selected from among the plurality of word lines; and
control logic configured to control the peripheral circuit to apply a turn-on voltage to a block word line coupled to the selected word line when the sensing operation is terminated and when potentials of the plurality of word lines are increased due to a recovery operation for channels of the plurality of memory cells after the plurality of word lines have been discharged.

2. The memory device according to claim 1 further including a transistor coupled to the block word line, wherein the turn-on voltage is a voltage for turning on the transistor.

3. The memory device according to claim 1 , wherein the turn-on voltage has a voltage level lower than a voltage level applied to the block word line during the sensing operation.

4. The memory device according to claim 1 , wherein the control logic is configured to control the peripheral circuit to, during an idle state after the sensing operation has been terminated, apply the turn-on voltage to the block word line for a reference time interval.

5. The memory device according to claim 4 , wherein the reference time interval is included in a time period corresponding to the idle state.

6. The memory device according to claim 1 , wherein the control logic is configured to control the peripheral circuit to, when the turn-on voltage is applied to the block word line and the potentials of the plurality of word lines are then discharged, perform a subsequent sensing operation.

7. The memory device according to claim 6 , wherein the control logic is configured to control the peripheral circuit to, during an idle state after the subsequent sensing operation has been terminated, apply the turn-on voltage to a block word line coupled to a word line, among the plurality of word lines, on which the subsequent sensing operation was performed.

8. A memory device, comprising:
a memory cell array coupled to a plurality of word lines, wherein each word line is coupled to a plurality of memory cells;
a peripheral circuit configured to perform a sensing operation of sensing selected memory cells coupled to a selected word line selected from among the plurality of word lines;
an idle state sensor configured to determine whether the memory device is in an idle state in which no operation is being performed on the memory cell array and to generate status information;
a voltage controller configured to generate voltage information used to set a voltage level to apply to a block word line coupled to the selected word line; and
an operation signal generator configured to, when the sensing operation is terminated and when potentials of the plurality of word lines are increased due to a recovery operation for channels of the plurality of memory cells after the plurality of word lines have been discharged, generate an operation signal instructing a turn-on voltage to be applied to the block word line based on the status information and the voltage information.

9. The memory device according to claim 8 , wherein the idle state sensor is configured to determine whether the memory device is in the idle state based on a ready/busy signal or an internal signal and to generate the status information indicating whether the memory device is in the idle state.

10. The memory device according to claim 8 , wherein the voltage controller is configured to generate the voltage information when a recovery operation completion signal indicating that the recovery operation has been completed is received.

11. The memory device according to claim 8 , wherein the voltage controller is configured to generate the voltage information to include information about a voltage level lower than a voltage level applied to the block word line during the sensing operation.

12. The memory device according to claim 8 , wherein the operation signal generator is configured to, when the voltage information is received from the voltage controller and when the status information indicates the idle state, output the operation signal instructing the turn-on voltage to be applied to the block word line for a reference time interval in the idle state after the sensing operation has been terminated.

13. The memory device according to claim 12 , wherein the reference time interval is included in a time period corresponding to the idle state.

14. A method of operating a memory device, the memory device including a memory cell array coupled to a plurality of word lines, wherein each word line is coupled to a plurality of memory cells, the method comprising:
performing a sensing operation of sensing selected memory cells coupled to a selected word line selected from among the plurality of word lines;
discharging the plurality of word lines after the sensing operation has been performed;
performing a recovery operation on channels of the plurality of memory cells;
determining whether the memory device is in an idle state during which no operation is being performed on the plurality of memory cells after the recovery operation has been performed; and
applying a turn-on voltage to a block word line coupled to the selected word line in the idle state.

15. The method according to claim 14 , wherein applying the turn-on voltage comprises applying the turn-on voltage to a transistor coupled to the block word line.

16. The method according to claim 14 , wherein applying the turn-on voltage comprises applying a voltage, to the block word line in the idle state, having a voltage level lower than a voltage level applied to the block word line during the sensing operation.

17. The method according to claim 14 , wherein applying the turn-on voltage to the block word line comprises applying the turn-on voltage to the block word line for a reference time interval in the idle state.

18. The method according to claim 17 , wherein the reference time interval is included in a time period corresponding to the idle state.

19. The method according to claim 14 further comprising performing a subsequent sensing operation after potentials of the plurality of word lines are discharged by applying the turn-on voltage to the block word line.

20. The method according to claim 19 further comprising applying, in an idle state after the subsequent sensing operation has been terminated, the turn-on voltage to a block word line coupled to a word line, among the plurality of word lines, on which the subsequent sensing operation was performed.

Assignees

• Sk Hynix Inc

Inventors

• Choi Gil Bok
• Yun dae hwan

Classifications

• G11C11/5671

  using charge trapping in an insulator · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C16/30

  Power supply circuits · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title