Method for preventing differential cryptanalysis attack

Patent metadata

Field	Value
Publication number	US-11520934-B2
Application number	US-202117614334-A
Country	US
Kind code	B2
Filing date	Mar 12, 2021
Priority date	Oct 28, 2020
Publication date	Dec 6, 2022
Grant date	Dec 6, 2022

Abstract

A method for preventing a differential cryptanalysis attack is provided. The method is implemented by an adaptive scan chain, a control module, and a plaintext analysis module. The plaintext analysis module controls the adaptive scan chain, so that two plaintexts differing in the last bit of only one byte are input through scan chains with different structures. Consequently, the two input plaintexts for which differential cryptanalysis attack technology originally can be used to crack the key are unable to generate outputs that can be used by the differential cryptanalysis attack technology.

First claim

What is claimed is:

1. A method for preventing a differential cryptanalysis attack, wherein
the method is implemented by an adaptive scan chain, a control module, and a plaintext analysis module;
the adaptive scan chain changes in structure according to a signal output by the plaintext analysis module; when an output value from the plaintext analysis module is 0, the adaptive scan chain is a common scan chain; and when the output value from the plaintext analysis module is 1, the adaptive scan chain is a complex scan chain;
the control module controls the plaintext analysis module to work only in a test mode; and
the plaintext analysis module is determined by the control module to work or not, and in a process of each round of plaintext analysis by the plaintext analysis module, once it is detected that input plaintexts differ in the last bit of only one byte, the output value is changed to change the structure of the adaptive scan chain;
and the method comprises the following steps:
step 1: detecting, by the control module, whether a chip switches to the test mode after being reset, and recording such a switch action, to determine whether to start the plaintext analysis module;
step 2: starting the plaintext analysis module, analyzing the plaintexts input to the chip, and changing the structure of a scan chain a currently input plaintext is about to go through if the currently input plaintext and a previously input plaintext meet a plaintext law for differential cryptanalysis; and
step 3: because the adaptive scan chain is able to change into a common scan chain or a complex scan chain, if the plaintext analysis module regards that the currently input plaintext has a risk of leaking key information, allowing the currently input plaintext to go through the complex scan chain; and if there is no risk after analysis, allowing the currently input plaintext to go through the common scan chain,
wherein the control module determines whether the chip makes an action scan en=1 of entering the test mode after being reset, and records the action as long as it happens; and in a specific implementation, once it is detected that a scan mode signal is enabled, an output signal from this module is pulled up and then the plaintext analysis module is able to start working.

2. The method for preventing a differential cryptanalysis attack according to claim 1 , wherein a structure of the adaptive scan chain is controlled by a selector which receives the output value from the plaintext analysis module; when a select signal is 0, the original scan chain remains unchanged; and when the select signal is 1, the structure of the scan chain is changed.

3. The method for preventing a differential cryptanalysis attack according to claim 1 , wherein the plaintext analysis module is enabled only in the test mode and stops working only when the chip is powered down.

Assignees

• Univ Nanjing Posts & Telecommunications
• Nantong Institute Of Nanjing Univ Of Posts And Telecommunications Co Ltd

Inventors

• Cai Zhikuang
• Xu Xun
• Wang Ming
• Wang Zixuan
• Wang Henglu
• Yao Jingqi
• Yao Jiafei
• Guo Yufeng

Classifications

• G06F21/75 Primary

  by inhibiting the analysis of circuitry or operation · CPC title