Systems and methods for using not perfectly polarized bit channels in parallel polar codes

Patent metadata

Field	Value
Publication number	US-11515964-B2
Application number	US-202117163100-A
Country	US
Kind code	B2
Filing date	Jan 29, 2021
Priority date	Jan 29, 2021
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

The disclosed systems, structures, and methods are directed to encoding and decoding information for transmission across a communication channel. The encoding method includes: distributing the information bits between m parallel polar codes such that each of the m parallel polar codes includes a subset of the information bits; splitting the subset of information bits in each of the m parallel polar codes into a protected information section and a full rate information section; protecting information bits in the protected information section of each of the m parallel polar codes; arranging a plurality of frozen bits in each of the m parallel polar codes; and generating a polar encoded codeword for each of the m parallel polar codes.

First claim

The invention claimed is:

1. A method for encoding information bits for transmission across a communication channel, the method comprising:
distributing the information bits between m parallel polar codes such that each of the m parallel polar codes includes a subset of the information bits, wherein m is the number of parallel polar codes;
splitting the subset of information bits in each of the m parallel polar codes into a protected information section and a full rate information section, information bits in the protected information section of each of the m parallel polar codes being arranged in positions in non-perfectly polarized bit channels in the respective parallel polar code of the m parallel polar codes and grouped into a plurality of L blocks, wherein each of the plurality of L blocks comprises a subset of the information bits in the protected information section for each of the m parallel polar codes, wherein L is the number of blocks;
protecting the information bits in the protected information section of each of the m parallel polar codes;
arranging a plurality of frozen bits in each of the m parallel polar codes; and
generating a polar encoded codeword for each of the m parallel polar codes.

2. The method of claim 1 , wherein the information bits in the protected information section of each of the m parallel polar codes are protected using a repetition code.

3. The method of claim 2 , wherein the information bits in a block of the plurality of L blocks of a first parallel polar code from the m parallel polar codes are repeated in a block of the plurality of L blocks of a second parallel polar code from the m parallel polar codes.

4. The method of claim 3 , wherein the information bits in a block of the plurality of L blocks of a first parallel polar code from the m parallel polar codes are repeated d i times in the m parallel polar codes, d i being a factor of m and greater than one.

5. The method of claim 1 , wherein a total number of the plurality of blocks in the non-perfectly polarized bit channels in each of the m parallel polar codes is determined based on a total number of greater-than-one factors of m.

6. A method for decoding m polar coded codewords received over a communication channel, each of the m polar coded codewords encoding information bits in a plurality of nodes, wherein m is the number of polar coded codewords, the method comprising:
for each node in each codeword from the m polar coded codewords:
when the node is in a full rate information section: decoding the node based on a log-likelihood ratio (LLR) decoding algorithm to generate a first part of a decoded message; and
when the node is in a protected information section: decoding the node based on an averaged LLR decoding algorithm to generate a second part of the decoded message.

7. The method of claim 6 , further comprising, for each of the m polar coded codewords: when a bit in the respective codeword is a frozen bit, generating a decoded bit in the decoded message based on a predetermined value.

8. The method of claim 6 , wherein the decoding of the node is performed by a successive-cancellation (SC) or a successive-cancellation-list (SCL).

9. The method of claim 6 , wherein the averaged LLR decoding algorithm is based on:

LLR
k
n

=

1
K

⁢

∑

j
=

(

k
-
1

)

*

d
i

+
1

k
*

d
i

LLR
j
o

where

≤
k
≤

m

d
i

,

d i is a total number of repetitions for the node in the m polar coded codewords, n represents that LLR k n are new modified LLRs, and LLR j o is the original LLR of the node in the respective codeword j in the m polar coded codewords, j=1 . . . m, K represents that the number of LLRs that are involved in averaging, and “*” here indicates the mathematical operation of multiplication.

10. An encoder that encodes information bits for transmission across a communication channel, the encoder comprising circuitry configured to:
distribute the information bits between m parallel polar codes such that each of the m parallel polar codes includes a subset of the information bits, wherein m is the number of parallel polar codes;
split the subset of information bits in each of the m parallel polar codes into a protected information section and a full rate information section, information bits in the protected information section of each of the m parallel polar codes being arranged in positions in non-perfectly polarized bit channels in the respective parallel polar code of the m parallel polar codes and grouped into a plurality of L blocks, wherein each of the plurality of L blocks comprises a subset of the information bits in the protected information section, wherein L is the number of blocks;
protect the information bits in the protected information section of each of the m parallel polar codes;
arrange a plurality of frozen bits in each of the m parallel polar codes; and
generate a polar encoded codeword for each of the m parallel polar codes.

11. The encoder of claim 10 , wherein the circuitry comprises at least one processor and a memory storing programmed instructions that when executed by the at least one processor cause the at least one processor to encode the information bits.

12. The encoder of claim 10 , wherein the information bits in the protected information section of each of the m parallel polar codes are protected using a repetition code.

13. The encoder of claim 12 , wherein the information bits in a block of the plurality of L blocks of a first parallel polar code from the m parallel polar codes are repeated in a block of the plurality of L blocks of a second parallel polar code from the m parallel polar codes.

14. The encoder of claim 13 , wherein the information bits in a block of the plurality of L blocks of a first parallel polar code from the m parallel polar codes are repeated d i times in the m parallel polar codes, d i being a factor of m and greater than one.

15. A decoder that decodes m polar coded codewords received

Assignees

• Ebrahimzad Hamid
• Zhang Zhuhong
• Huawei Tech Co Ltd

Inventors

• Ebrahimzad Hamid
• Zhang Zhuhong

Classifications

• H04L1/0041 Primary

  Arrangements at the transmitter end · CPC title

• H04L1/0065

  Serial concatenated codes · CPC title

• H03M13/6561

  Parallelized implementations · CPC title

• H04L1/0057

  Block codes (H04L1/0061, H04L1/0064 take precedence) · CPC title

• H03M13/13

  Linear codes · CPC title