EMI reduction in piezoelectric micromachined ultrasound transducer array

US11515465B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11515465-B2
Application numberUS-201916281792-A
CountryUS
Kind codeB2
Filing dateFeb 21, 2019
Priority dateFeb 26, 2018
Publication dateNov 29, 2022
Grant dateNov 29, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A piezoelectric micromachined ultrasound transducer (PMUT) array may comprise PMUT devices with respective piezoelectric layers and electrode layers. Parasitic capacitance can be reduced when an electrode layer is not shared across PMUT devices but may expose the devices to electromagnetic interference (EMI). A conductive layer located within the structural layer or on a shared plane with the electrode layers may reduce EMI affecting the PMUT array operation.

First claim

Opening claim text (preview).

What is claimed is: 1. An array of piezoelectric micromachined ultrasound transducer (PMUT) devices, comprising: an electrical component layer; a plurality of PMUT transceivers, wherein each of the plurality of PMUT transceivers comprises: a piezoelectric layer and a structural layer, wherein the piezoelectric layer is located between the electrical component layer and the structural layer; a first electrode electrically connected to the electrical component layer and the piezoelectric layer, wherein the first electrode is located between the structural layer and the piezoelectric layer; and a second electrode electrically connected to the electrical component layer and the piezoelectric layer, wherein the second electrode is located between the electrical component layer and the piezoelectric layer; and a conductive layer located above the piezoelectric layer and within the structural layer. 2. The array of PMUT devices of claim 1 , wherein the conductive layer at least partially covers the structural layer. 3. The array of PMUT devices of claim 2 , wherein the conductive layer at least partially covers an upper surface of the structural layer. 4. The array of PMUT devices of claim 3 , wherein the conductive layer substantially covers all of the upper surface of the structural layer. 5. The array of PMUT devices of claim 3 , wherein the conductive layer comprises an electromagnetic interference (EMI) layer. 6. The array of PMUT devices of claim 5 , further comprising an oxide layer between the structural layer and the EMI layer. 7. The array of PMUT devices of claim 6 , further comprising a passivation layer covering the EMI layer. 8. The array of PMUT devices of claim 3 , wherein the conductive layer comprises a patterned layer. 9. The array of PMUT devices of claim 8 , wherein the patterned layer comprises a plurality of slots at least partially covering the upper surface of the structural layer. 10. The array of PMUT devices of claim 1 , wherein the conductive layer comprises a ground shield. 11. The array of PMUT devices of claim 1 , wherein the conductive layer comprises a ground mesh. 12. The array of PMUT devices of claim 1 , wherein the conductive layer is located between the piezoelectric layer and the structural layer. 13. The array of PMUT devices of claim 12 , wherein the conductive layer is located in a shared plane with the first electrodes. 14. The array of PMUT devices of claim 12 , wherein the conductive layer comprises a patterned layer. 15. The array of PMUT devices of claim 1 , wherein each of the plurality of PMUT transceivers is configured to operate in either a transmit mode or a receive mode. 16. The array of PMUT devices of claim 1 , wherein the electrical component layer comprises a CMOS layer. 17. An array of piezoelectric micromachined ultrasound transducer (PMUT) devices, comprising: an electrical component layer; a plurality of PMUT transceivers, wherein each of the plurality of PMUT transceivers comprises: a piezoelectric layer and a structural layer, wherein the piezoelectric layer is located between the electrical component layer and the structural layer; a first electrode electrically connected to the electrical component layer and the piezoelectric layer, wherein the first electrode is located between the structural layer and the piezoelectric layer; a second electrode electrically connected to the electrical component layer and the piezoelectric layer, wherein the second electrode is located between the electrical component layer and the piezoelectric layer; and a conductive layer located in a shared plane with the second electrode. 18. The array of PMUT devices of claim 17 , wherein the conductive layer comprises an electromagnetic interference layer. 19. The array of PMUT devices of claim 17 , wherein the conductive layer comprises a patterned layer. 20. The array of PMUT devices of claim 17 , wherein the conductive layer comprises a ground mesh.

Assignees

Inventors

Classifications

  • for protecting against electromagnetic or electrostatic interferences · CPC title

  • Transducers for transforming electrical into mechanical energy or vice versa (dynamo-electric machines H02K99/00; electrostatic machines H02N1/00; piezoelectric devices H10N30/00) · CPC title

  • with foil-type piezoelectric elements, e.g. PVDF · CPC title

  • B06B1/0622Primary

    on one surface · CPC title

  • non-optical, e.g. ultrasonic or capacitive sensing · CPC title

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Frequently asked questions

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What does patent US11515465B2 cover?
A piezoelectric micromachined ultrasound transducer (PMUT) array may comprise PMUT devices with respective piezoelectric layers and electrode layers. Parasitic capacitance can be reduced when an electrode layer is not shared across PMUT devices but may expose the devices to electromagnetic interference (EMI). A conductive layer located within the structural layer or on a shared plane with the e…
Who is the assignee on this patent?
Invensense Inc
What technology area does this patent fall under?
Primary CPC classification B06B1/0622. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Nov 29 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).