3D NAND structures with decreased pitch

Patent metadata

Field	Value
Publication number	US-11515324-B2
Application number	US-201916720643-A
Country	US
Kind code	B2
Filing date	Dec 19, 2019
Priority date	Dec 19, 2018
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with increased cell density. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells. Some embodiments form 3D NAND devices with smaller CD memory holes. Some embodiments form 3D NAND devices with silicon layer between alternating oxide and nitride materials.

First claim

What is claimed is:

1. A method of forming a 3D NAND device, the method comprising:
depositing a layer of an oxide material, a first silicon layer directly on the oxide material, a nitride material directly on the first silicon layer, and a second silicon layer directly on the nitride material;
repeating deposition of the oxide material, the first silicon layer, the nitride material and the second silicon layer to deposit a plurality of alternating layers of the nitride material and the oxide material;
etching a memory hole with a width through the plurality of alternating layers to form an exposed surface of the plurality of alternating layers;
selectively etching a portion of the nitride material;
depositing a blocking oxide layer, a charge trap nitride layer and a gate oxide layer in the memory hole to form a liner on the exposed surface of the plurality of alternating layers;
depositing a silicon material to fill the memory hole;
etching a slit through the plurality of alternating layers;
removing the nitride material to expose the first and second silicon layers and form a gap;
removing the first and second silicon layers to expose the layers of oxide material; and
depositing a metal gate material to fill the gap between the layers of oxide material.

2. The method of claim 1 , wherein the plurality of alternating layers are deposited by chemical vapor deposition.

3. The method of claim 1 , wherein a layer of the nitride material has a thickness of about 27 nm, the first and second silicon layers have a thickness of about 3 nm, and a layer of the oxide material has a thickness of about 25 nm.

4. The method of claim 1 , wherein the width of the memory hole is about 70 nm.

5. The method of claim 1 , wherein selectively etching a portion of the nitride material comprises an atomic layer etching process.

6. The method of claim 1 , wherein the nitride material is etched to remove a depth in a range of about 10% to about 20% of the width of the memory hole.

7. The method of claim 1 , wherein the liner is substantially conformal to the exposed surface of the plurality of alternating layers.

8. The method of claim 1 , wherein the blocking oxide layer, the charge trap nitride layer and the gate oxide layer are deposited by a spatial atomic layer deposition process.

9. The method of claim 1 , wherein the silicon material is deposited by chemical vapor deposition, epitaxial deposition or flowable chemical vapor deposition.

10. The method of claim 1 , wherein the nitride material is removed by hot phosphoric acid.

11. The method of claim 1 , wherein the silicon layers are removed by potassium hydroxide.

12. The method of claim 1 , further comprising depositing a barrier layer on the layers of oxide material after the silicon layers are removed.

13. The method of claim 12 , wherein the barrier layer is deposited by atomic layer deposition.

14. The method of claim 12 , wherein the barrier layer comprises titanium nitride.

15. The device formed by the method of claim 1 .

16. A method for reducing interfacial SiON in 3D NAND devices, the method comprising:
forming a plurality of alternating layers of a nitride material and an oxide material by a cycle comprising:
depositing a nitride material layer;
depositing a first layer of silicon material directly on the nitride material layer;
depositing an oxide material layer directly on the first layer of silicon material; and

depositing a second layer of silicon material directly on the oxide material layer;
repeating the cycle to form a predetermined number of layers; and
forming a 3D NAND device.

17. The method of claim 16 , wherein forming the 3D NAND device comprises:
etching a memory hole through the plurality of alternating layers;
depositing a blocking oxide layer, a charge trap nitride layer and a gate oxide layer in the memory hole;
depositing a silicon material to fill the memory hole; and
replacing the nitride material with a metal gate material.

Assignees

• Applied Materials Inc

Inventors

• Kwon Thomas
• Han Xinhai

Classifications

• H01L29/518

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title