Circuit including configuration terminal and method

Patent metadata

Field	Value
Publication number	US-11515302-B2
Application number	US-202016879188-A
Country	US
Kind code	B2
Filing date	May 20, 2020
Priority date	May 21, 2019
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

A circuit includes a switch coupled between a configuration terminal and an internal node. In a method of operation, the configuration terminal of the circuit is coupled to an internal node during a configuration phase and decoupled from the internal node during normal operation.

First claim

What is claimed is:

1. A circuit comprising:
a configuration terminal configured to receive configuration signals in a configuration phase of the circuit;
an internal node coupled to internal circuitry of the circuit;
a first switch coupled between the configuration terminal and the internal node, wherein the first switch is configured to couple the configuration terminal with the internal node during the configuration phase and to decouple the configuration terminal from the internal node during normal operation of the circuit;
a capacitor coupled between a control terminal of the first switch and a reference potential; and
a second switch directly coupled between the internal node and the reference potential, wherein the second switch is configured to couple the internal node to a reference potential during the normal mode of operation and to decouple the internal node from the reference potential in the configuration phase.

2. The circuit of claim 1 , wherein the first switch comprises a transmission gate including a PMOS transistor and an NMOS transistor.

3. The circuit of claim 2 , further comprising an RC filter configured to couple a well of the PMOS transistor to a reference potential and/or an RC filter configured to couple a well of the NMOS transistor to the reference potential.

4. The circuit of claim 1 , further comprising ESD protection circuitry coupled to the internal node.

5. The circuit of claim 1 , further comprising control circuitry configured to control the first switch and/or the second switch.

6. The circuit of claim 1 , further comprising further terminals configured to control the first switch and/or the second switch.

7. The circuit of claim 1 , further comprising a radio frequency terminal configured to receive radio frequency signals adjacent to the configuration terminal.

8. The circuit of claim 1 , wherein the capacitor comprises an integrated circuit capacitor.

9. A method, comprising:
coupling a configuration terminal to an internal node of a circuit during a configuration phase;
decoupling the configuration terminal from the internal node during normal operation; and
capacitively coupling the configuration terminal or the internal node to a reference potential,
wherein the method is performed using a circuit comprising a first switch coupled between the configuration terminal and the internal node, and a second switch directly coupled between the internal node and the reference potential.

10. The method of claim 9 , further comprising coupling the internal node to a reference potential during normal operation, and decoupling the internal node from the reference potential during the configuration phase.

11. The method of claim 9 , further comprising applying a radio frequency signal to a further terminal of the circuit during normal operation.

12. The method of claim 9 , further comprising coupling ESD protection circuitry to the internal node.

13. The method of claim 9 , wherein capacitively coupling the configuration terminal or the internal node to a reference potential comprises capacitively coupling the configuration terminal or the internal node to the reference potential with an integrated circuit capacitor.

14. A circuit comprising:
a configuration terminal;
an internal node coupled to internal circuitry of the circuit;
a first switch having a current path and a first control node configured for receiving an externally generated first control signal, wherein the current path is directly coupled between the configuration terminal and the internal node; and
a capacitor coupled between a control terminal of the first switch and a reference potential; and
a second switch having a current path and a second control node not directly connected to the first control node, wherein the second control node is configured for directly receiving an externally generated second control signal, and wherein the current path is directly coupled between the internal node and the reference potential.

15. The circuit of claim 14 , wherein the first switch comprises a transmission gate including a PMOS transistor and an NMOS transistor.

16. The circuit of claim 15 , further comprising an RC filter configured to couple a well of the PMOS transistor to a reference potential and/or an RC filter configured to couple a well of the NMOS transistor to the reference potential.

17. The circuit of claim 15 , further comprising ESD protection circuitry coupled to the internal node.

18. The circuit of claim 15 , further comprising control circuitry configured to control the first switch and/or the second switch.

19. The circuit of claim 14 , further comprising a radio frequency terminal adjacent to the configuration terminal.

20. The circuit of claim 14 , wherein the capacitor comprises an integrated circuit capacitor.

Assignees

• Infineon Technologies Ag

Inventors

• Bakalski Winfried
• Baenisch Andreas

Classifications

• H03K19/00361

  in field effect transistor circuits · CPC title

• H02H9/046

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H03K19/00315

  in field-effect transistor circuits · CPC title

• H05K9/00

  Screening of apparatus or components against electric or magnetic fields (devices for absorbing radiation from an antenna H01Q17/00) · CPC title

• H03K19/017545 Primary

  Coupling arrangements; Impedance matching circuits · CPC title