Semiconductor processing chamber multistage mixing apparatus

Patent metadata

Field	Value
Publication number	US-11515179-B2
Application number	US-202016915749-A
Country	US
Kind code	B2
Filing date	Jun 29, 2020
Priority date	Feb 15, 2018
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

Exemplary semiconductor processing systems may include a processing chamber, and may include a remote plasma unit coupled with the processing chamber. Exemplary systems may also include a mixing manifold coupled between the remote plasma unit and the processing chamber. The mixing manifold may be characterized by a first end and a second end opposite the first end, and may be coupled with the processing chamber at the second end. The mixing manifold may define a central channel through the mixing manifold, and may define a port along an exterior of the mixing manifold. The port may be fluidly coupled with a first trench defined within the first end of the mixing manifold. The first trench may be characterized by an inner radius at a first inner sidewall and an outer radius, and the first trench may provide fluid access to the central channel through the first inner sidewall.

First claim

The invention claimed is:

1. A semiconductor processing system component comprising:
a mixing manifold comprising a body characterized by a first surface and a second surface opposite the first surface, the mixing manifold defining a central channel through the mixing manifold extending from the first surface through the second surface, wherein the central channel comprises an inlet end upstream of an outlet end, wherein the inlet end extends through the first surface and the outlet end extends through the second surface, wherein the mixing manifold defines a first trench defined within the first surface of the mixing manifold, wherein the first trench is characterized by an inner radius at a first inner sidewall and an outer radius, wherein the first inner sidewall defines a plurality of apertures through the first inner sidewall, and wherein the first trench provides fluid access to the central channel through the plurality of apertures defined in the first inner sidewall.

2. The semiconductor processing system component of claim 1 , further comprising a port defined in the mixing manifold proximate the first surface, wherein the port is fluidly coupled with the first trench.

3. The semiconductor processing system component of claim 1 , wherein the mixing manifold further comprises a second trench defined within the mixing manifold, wherein the second trench is located radially outward from the first trench.

4. The semiconductor processing system component of claim 3 , wherein the second trench is characterized by an inner radius at a second inner sidewall, and wherein the second inner sidewall further defines the outer radius of the first trench.

5. The semiconductor processing system component of claim 4 , wherein the second inner sidewall defines a plurality of apertures through the second inner sidewall and providing fluid access to the first trench.

6. The semiconductor processing system component of claim 5 , wherein each aperture of the plurality of apertures defined through the second inner sidewall are radially offset from each aperture of the plurality of apertures defined through the first inner sidewall.

7. The semiconductor processing system component of claim 5 , wherein two apertures are defined through the second inner sidewall at opposite ends of a diameter through the second inner sidewall.

8. The semiconductor processing system component of claim 7 , wherein a port is defined by the mixing manifold equidistantly between the two apertures defined through the second inner sidewall.

9. The semiconductor processing system component of claim 1 , wherein at least three apertures are defined in the first inner sidewall, and wherein the apertures are distributed equidistantly about the first inner sidewall.

10. The semiconductor processing system component of claim 1 , wherein the first inner sidewall is characterized by a chamfered edge.

11. The semiconductor processing system component of claim 10 , wherein the plurality of apertures defined in the first inner sidewall are defined through the chamfered edge of the first inner sidewall.

12. The semiconductor processing system component of claim 11 , wherein the plurality of apertures are defined at an angle through the first inner sidewall.

13. The semiconductor processing system component of claim 1 , wherein the mixing manifold comprises nickel.

14. The semiconductor processing system component of claim 13 , wherein the nickel is nickel plating.

15. A semiconductor processing system component comprising:
a mixing manifold comprising a body characterized by a first surface and a second surface opposite the first surface, the mixing manifold defining a central channel through the mixing manifold extending from the first surface through the second surface, wherein the central channel comprises an inlet end upstream of an outlet end, wherein the inlet end extends through the first surface and the outlet end extends through the second surface, wherein the mixing manifold defines a port along an exterior wall of the mixing manifold between the first surface and the second surface, wherein the port is fluidly coupled with a first trench defined within the first surface of the mixing manifold, wherein the first trench is characterized by an inner radius at a first inner sidewall and an outer radius, wherein the first trench provides fluid access to the central channel through the first inner sidewall, wherein the mixing manifold further defines a second trench, wherein the second trench is located radially outward from the first trench, and wherein the port is fluidly coupled with the second trench.

16. The semiconductor processing system component of claim 15 , wherein the second trench is characterized by an inner radius at a second inner sidewall, and wherein the second inner sidewall further defines the outer radius of the first trench.

17. The semiconductor processing system component of claim 16 , wherein the second inner sidewall defines a plurality of apertures defined through the second inner sidewall and providing fluid access to the first trench.

18. The semiconductor processing system component of claim 17 , wherein the second inner sidewall defines two apertures through the second inner sidewall, and wherein the first inner sidewall defines a plurality of apertures defined through the first inner sidewall, and wherein each aperture defined through the second inner sidewall is radially offset from each aperture of the plurality of apertures defined through the first inner sidewall.

19. A semiconductor processing system component comprising:
a mixing manifold comprising a body characterized by a first surface and a second surface opposite the first surface, the mixing manifold defining a central channel through the mixing manifold extending from the first surface to the second surface, wherein the central channel comprises an inlet end upstream of an outlet end, wherein the inlet end extends through the first surface and the outlet end extends through the second surface, wherein the mixing manifold defines a port along a sidewall of the mixing manifold extending between the first surface and the second surface, wherein the port is fluidly coupled with a first trench defined within the first surface of the mixing manifold, wherein the first trench is characterized by an inner radius at a first inner sidewall and an outer radius, wherein the first trench provides fluid access to the central channel through the first inner sidewall, wherein the first inner sidewall defines at least three apertures through the first inner sidewall, and wherein the apertures are distributed equidistantly about the first inner sidewall.

20. The semiconductor processing system component of claim 19 , wherein the mixing manifold further comprises a second trench defined within the mixing manifold, wherein the second trench is located radially outward from the first trench.

Assignees

• Applied Materials Inc

Inventors

• Samir Mehmet Tugrul
• Yang Dongqing

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P72/0421 Primary

  for drying etching · CPC title

• B01F2101/58

  Mixing semiconducting materials, e.g. during semiconductor or wafer manufacturing processes · CPC title

• B01F25/31423 Primary

  with a plurality of perforations in the circumferential direction only and covering the whole circumference · CPC title

• B01F25/105

  Mixing heads, i.e. compact mixing units or modules, using mixing valves for feeding and mixing at least two components · CPC title