Display apparatus and multi-screen display apparatus including the same

Patent metadata

Field	Value
Publication number	US-11514859-B2
Application number	US-202017138013-A
Country	US
Kind code	B2
Filing date	Dec 30, 2020
Priority date	Dec 31, 2019
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

A display apparatus and a multi-screen display apparatus including the display apparatus are provided. The display apparatus includes a substrate including a display portion, a plurality of pixels connected to a gate line and a data line disposed in the display portion, and a gate driving circuit disposed in the display portion to drive the gate line. The gate driving circuit includes a stage circuit unit including a plurality of stage circuits respectively disposed in a plurality of division regions defined in the display portion, and a circuit repair portion configured to repair at least one of the plurality of stage circuits.

First claim

What is claimed is:

1. A display apparatus comprising:
a substrate including a display portion;
a plurality of pixels connected to a gate line and a data line disposed in the display portion; and
a gate driving circuit disposed in the display portion to drive the gate line, wherein the gate driving circuit comprises:
a stage circuit unit including a plurality of stage circuits respectively disposed in a plurality of division regions defined in the display portion; and
a circuit repair portion configured to repair at least one of the plurality of stage circuits,

wherein each of the plurality of stage circuits comprises:
a plurality of branch circuits disposed separately between the plurality of pixels, in the plurality of division regions of the display portion; and
a branch network connected to the gate line to electrically connect the plurality of branch circuits, and

wherein the circuit repair portion is disposed between the plurality of stage circuits and overlaps the branch network of an adjacent stage circuit.

2. The display apparatus of claim 1 , wherein each of the plurality of branch circuits comprises at least one thin film transistor.

3. The display apparatus of claim 2 , further comprising a gate control line group disposed separately between the plurality of pixels in the display portion,
wherein the branch network comprises:
a plurality of control nodes disposed in parallel with the gate line; and
a network line connected between the plurality of branch circuits and selectively connected to lines of the gate control line group and the plurality of control nodes, and

wherein the circuit repair portion is disposed between the plurality of stage circuits and overlaps each of a plurality of control nodes disposed in adjacent stage circuits.

4. The display apparatus of claim 3 , wherein the circuit repair portion comprises a plurality of node repair patterns electrically disconnected from one another to respectively overlap a plurality of control nodes disposed in adjacent stage circuits.

5. The display apparatus of claim 4 , wherein the circuit repair portion is electrically connected to at least one of the plurality of control nodes disposed in the adjacent stage circuits, and
wherein at least one of the plurality of branch circuits disposed in one of the adjacent stage circuits is electrically disconnected from a corresponding control node connected to the circuit repair portion.

6. The display apparatus of claim 1 , wherein each of a plurality of branch circuits disposed in one of two adjacent stage circuits is electrically disconnected from the branch network, and
wherein a branch network disposed in one of the two adjacent stage circuits is electrically connected to a branch network disposed in the other stage circuit of the two adjacent stage circuits through the circuit repair portion.

7. The display apparatus of claim 1 , further comprising a gate control line group disposed separately between the plurality of pixels in the display portion and connected to each of the plurality of stage circuits,
wherein the branch network comprises:
a first control node, a second control node, and a third control node disposed in parallel with the gate line; and
a network line selectively connected to the gate control line group and selectively connected to the first to third control nodes, and

wherein each of the plurality of stage circuits comprises:
a node control circuit controlling a voltage of each of the first to third control nodes;
a first inverter circuit controlling the voltage of the second control node based on the voltage of the first control node;
a second inverter circuit controlling the voltage of the third control node based on the voltage of the first control node; and
an output buffer circuit outputting the scan signal based on the voltage of each of the first to third control nodes.

8. The display apparatus of claim 7 , wherein a plurality of thin film transistors, respectively included in the node control circuit, the first inverter circuit, the second inverter circuit, and the output buffer circuit, are separately disposed in one horizontal line and configure each of the plurality of branch circuits.

9. The display apparatus of claim 1 , further comprising:
a rear substrate coupled to a rear surface of the substrate by using a coupling member;
a routing portion including a routing line disposed on an outer surface of the substrate and an outer surface of the rear substrate; and
a driving circuit unit disposed on the rear substrate,
wherein the substrate further comprises a first pad part including a plurality of pads connected to the data line and the gate driving circuit and electrically connected to the routing line of the routing portion, and
wherein the rear substrate comprises:
a second pad part electrically connected to the routing line of the routing portion to overlap the first pad part; and
a third pad part electrically connected to the second pad part and connected to the driving circuit unit.

10. The display apparatus of claim 1 , wherein a side surface of the display portion is aligned on an outer surface of the substrate, or a size of the display portion is the same as a size of the substrate.

11. A multi-screen display apparatus comprising:
a plurality of display modules arranged in at least one direction of a first direction and a second direction transverse to the first direction,
wherein each of the plurality of display modules comprises the display apparatus of claim 1 .

12. The multi-screen display apparatus of claim 11 , wherein each of the plurality of display modules further comprises:
a rear substrate coupled to a rear surface of the substrate by using a coupling member;
a routing portion including a routing line disposed on an outer surface of the substrate and an outer surface of the rear substrate; and
a driving circuit unit disposed on the rear substrate,
wherein the substrate further comprises a first pad part including a plurality of pads connected to the data line and the gate driving circuit and electrically connected to the routing line of the routing portion, and
wherein the rear substrate comprises:
a second pad part electrically connected to the routing line of the routing portion to overlap the first pad part; and
a third pad part electrically connected to the second pad part and connected to the driving circuit unit.

13. The multi-screen display apparatus of claim 12 , wherein an outermost pixel of the plurality of pixels comprises the plurality of pads, or
wherein the plurality of pixels are arranged on the substrate to have a pixel pitch in the first direction and the second direction transverse to the first direction, and an interval between a center portion of the outermost pixel and the outer surface of the substrate is equal to or less than half of the pixel pitch.

14. A display apparatus comprising:
a substrate including a display portion;
a plurality of pixels connected to a gate line and a data line disposed in the display portion; and
a gate driving circuit disposed in the display portion to drive the gate line,
wherein the gate driving circuit comprises:
a stage circuit unit including a plurality of stage circuits respectively disposed in a plurality of division regions defined in the display portion; and
a circuit repair portion configured to repair at least one of the plurality of stage circuits,

wherein each of the plurality of stage circuits comprises:
a plurality of branch circuits disposed separately between the plurality of pixels, in the plurality of division regions of the displa

Assignees

• Lg Display Co Ltd

Inventors

• Jang Youngin
• Kim Kyungmin
• Kim Hyundong

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0264

  Details of driving circuits · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title