Pixel drive circuit, pixel unit, driving method, array substrate, and display apparatus

Patent metadata

Field	Value
Publication number	US-11514844-B2
Application number	US-202017424408-A
Country	US
Kind code	B2
Filing date	Sep 10, 2020
Priority date	Sep 12, 2019
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

A pixel drive circuit includes a data write sub-circuit, an input and read sub-circuit, a drive sub-circuit, and a first output control sub-circuit. The data write sub-circuit is configured to transmit data signals input from a first data voltage terminal at different times to a first node. The input and read sub-circuit is configured to: transmit a signal of a signal transmission terminal to a second node in a write period, and transmit an electrical signal of the second node to the signal transmission terminal in a threshold voltage read period. The drive sub-circuit is configured to output a drive signal. The first output control sub-circuit is configured to: be coupled to an element to be driven, and transmit the drive signal output by the drive sub-circuit to the element to be driven.

First claim

What is claimed is:

1. An array substrate, comprising a plurality of read signal lines, a plurality of transmission circuits, and a plurality of pixel units arranged in a matrix; wherein
each of the plurality of pixel units comprises a pixel drive circuit and an element to be driven, wherein
the pixel drive circuit comprises a data write sub-circuit, an input and read sub-circuit, a drive sub-circuit, and a first output control sub-circuit;
wherein the data write sub-circuit is coupled to a first node, a first scan signal terminal, and a first data voltage terminal, and the data write sub-circuit is configured to transmit data signals input from the first data voltage terminal at different times to the first node under control of a turn-on signal transmitted by the first scan signal terminal;
wherein the input and read sub-circuit is coupled to a second node, a first signal terminal and a signal transmission terminal, and the input and read sub-circuit is configured to: transmit a signal of the signal transmission terminal to the second node under control of a turn-on signal transmitted by the first signal terminal in a write period, and transmit an electrical signal of the second node to the signal transmission terminal under the control of the turn-on signal transmitted by the first signal terminal in a threshold voltage read period;
wherein the drive sub-circuit is coupled to the first node, the second node, and a first voltage terminal, and the drive sub-circuit is configured to output a drive signal under control of a signal of the first node, a signal of the second node, and a signal of the first voltage terminal; and
wherein the first output control sub-circuit is coupled to the drive sub-circuit and an enable signal terminal, and the first output control sub-circuit is configured to: be coupled to an element to be driven, and transmit the drive signal output by the drive sub-circuit to the element to be driven under control of a turn-on signal transmitted by the enable signal terminal; and
the element to be driven is coupled to a second voltage terminal and the first output control sub-circuit of the pixel drive circuit, and the element to be driven is configured to emit light under driving of the drive signal output by the pixel drive circuit through a signal path closed between the first voltage terminal and the second voltage terminal;

signal transmission terminals of pixel units located in a same column are coupled to a read signal line of the plurality of read signal lines, and the read signal line is coupled to a transmission circuit of the plurality of transmission circuits; and
the transmission circuit is configured to: input an initialization signal to a signal transmission terminal of each pixel unit of the pixel units located in the same column through the read signal line in the write period, and read a signal from the signal transmission terminal through the read signal line in the threshold voltage read period, wherein
the transmission circuit includes a seventh transistor; wherein a gate of the seventh transistor is coupled to a second signal terminal, a first electrode of the seventh transistor is coupled to the read signal line, a second electrode of the seventh transistor is configured to: receive the initialization signal under control of a signal of the second signal terminal in the write period, and output the signal of the read signal line in the threshold voltage read period; or
the transmission circuit includes an eighth transistor and a ninth transistor; wherein a gate of the eighth transistor is coupled to a third signal terminal, a first electrode of the eighth transistor is coupled to the read signal line, and a second electrode of the eighth transistor is configured to receive the initialization signal under control of a signal of the third signal terminal in the write period; and a gate of the ninth transistor is coupled to a fourth signal terminal, a first electrode of the ninth transistor is coupled to the read signal line, and a second electrode of the ninth transistor is configured to output the signal of the read signal line under control of a signal of the fourth signal terminal in the threshold voltage read period.

2. A display apparatus, comprising the array substrate according to claim 1 and an integrated circuit coupled to the read signal lines in the array substrate; wherein
the array substrate further includes a plurality of data lines coupled to the integrated circuit; and in the array substrate, data write sub-circuits of the pixel units located in the same column are coupled to a data line of the plurality of data lines; and
the integrated circuit is configured to: receive a signal of the read signal line, obtain a threshold voltage of a drive sub-circuit in the pixel unit, generate a compensated data signal, and transmit the compensated data signal to the data write sub-circuit through the data line in the threshold voltage read period.

3. The display apparatus according to claim 2 , wherein the array substrate further includes a plurality of first scan signal lines, a plurality of enable signal lines and a plurality of second scan signal lines; wherein
pixel drive circuits of pixel units located in a same row are coupled to a same first scan signal line, a same enable signal line, and a same second scan signal line.

4. A method of driving an array substrate, wherein the array substrate includes a plurality of read signal lines, a plurality of transmission circuits, and a plurality of pixel units arranged in a matrix; each pixel unit includes a pixel drive circuit and an element to be driven; wherein
the pixel drive circuit includes a data write sub-circuit, an input and read sub-circuit, a drive sub-circuit, and a first output control sub-circuit and a time control sub-circuit; wherein
the data write sub-circuit is coupled to a first node, a first scan signal terminal and a first data voltage terminal; the input and read sub-circuit is coupled to a second node, a first signal terminal and a signal transmission terminal; the drive sub-circuit is coupled to the first node, the second node and a first voltage terminal; the first output control sub-circuit is coupled to the drive sub-circuit, the element to be driven and an enable signal terminal; and the time control sub-circuit is coupled to a second scan signal terminal, a third voltage terminal, a second data voltage terminal, the first output control sub-circuit and the element to be driven; and

the element to be driven is coupled to the first output control sub-circuit and a second voltage terminal;
wherein signal transmission terminals of pixel units located in a same column are coupled to a read signal line of the plurality of read signal lines, and the read signal line is coupled to a transmission circuit of the plurality of transmission circuits;
the transmission circuit includes a seventh transistor, a gate of the seventh transistor is coupled to a second signal terminal, and a first electrode of the seventh transistor is coupled to the read signal line; or
the transmission circuit includes an eighth transistor and a ninth transistor; a gate of the eighth transistor is coupled to a third signal terminal, a first electrode of the eighth transistor is coupled to the read signal line; a gate of the ninth transistor is coupled to a fourth signal terminal, a first electrode of the ninth transistor is coupled to the read signal line;
a display period of the array substrate includes a write period, a time control period, and a light-emitting period, the method comprises:
in the write period,
transmitting, by the data write sub-circuit, a data signal input from the first data voltage terminal to the first node under control of a turn-on signal transmitted by the first scan signal terminal; and
transmitting, by the inp

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Xiao Li
• Xuan Minghua
• Liu Dongni
• Liu Jing
• Qi Qi
• Zheng Haoliang
• Zhang Zhenyu
• Chen Liang
• Chen Hao

Classifications

• G09G2310/0278

  Details of driving circuits arranged to drive both scan and data electrodes · CPC title

• G09G2230/00

  Details of flat display driving waveforms · CPC title

• G09G2320/0295

  by monitoring each display pixel · CPC title

• G09G2310/06

  Details of flat display driving waveforms · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title