Line interleaving controller, image signal processor and application processor including the same

Patent metadata

Field	Value
Publication number	US-11514552-B2
Application number	US-202017136494-A
Country	US
Kind code	B2
Filing date	Dec 29, 2020
Priority date	Jun 4, 2020
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

An image signal processor includes a line interleaving controller and an image signal processor core. The line interleaving controller receives a plurality of image data lines included in an image frame, generates one or more virtual data lines corresponding to the image frame, and outputs the plurality of image data lines and the virtual data lines sequentially line by line. The image signal processor core includes at least one pipeline circuit. The pipe line circuit includes a plurality of processing modules serially connected to sequentially process data lines received from the line interleaving controller. The line interleaving controller processes one or more end image data lines included in an end portion of the image frame based on the virtual data lines. Interference or collision between channels is reduced or prevented by processing the end image data lines in synchronization with the virtual data lines.

First claim

What is claimed is:

1. An image signal processor comprising:
a line interleaving controller configured to
receive a plurality of image data lines included in an image frame,
determine a number of virtual data lines based on module delay sizes of one or more delayed processing modules, each module delay size indicating a number of delay data lines of each delayed processing module,
generate the number of virtual data lines corresponding to the image frame, and
output the plurality of image data lines and the virtual data lines sequentially line by line; and
an image signal processor core including at least one pipeline circuit, the pipeline circuit including a plurality of processing modules serially connected to sequentially process data lines received from the line interleaving controller, the image signal processor core configured to process one or more end image data lines included in an end portion of the image frame based on the virtual data lines.

2. The image signal processor of claim 1 , wherein the plurality of processing modules include:
the one or more delayed processing modules, each configured to perform a delayed filtering operation on a target data line to be processed based on one or more delayed data lines received after the target data line.

3. The image signal processor of claim 2 , wherein the image signal processor core performs the delayed filtering operation on the end image data lines on the fly in synchronization with the virtual data lines received from the line interleaving controller, and the image signal processor receives data lines from the line interleaving controller while the image signal processor core performs the delayed filtering operation on the end image data lines.

4. The image signal processor of claim 2 , wherein the image signal processor core includes a single pipeline circuit, and
wherein the line interleaving controller generates and outputs the virtual data lines such that the number of the virtual data lines is equal to a sum of the module delay sizes of the delayed processing modules included in the single pipeline circuit.

5. The image signal processor of claim 2 , wherein each delayed processing module performs the delayed filtering operation on the end image data lines using a first number of received virtual data lines, and outputs a second number of the received virtual data lines without processing, the first number corresponding to the module delay size of the each delayed processing module, the second number corresponding to the received virtual data lines not used in the delayed filtering operation of the each delayed processing module.

6. The image signal processor of claim 2 , wherein the image signal processor core includes:
a first pipeline circuit including one or more first delayed processing modules; and
a second pipeline circuit including one or more second delayed processing modules, the first pipeline circuit being connected in parallel with the first pipeline circuit.

7. The image signal processor of claim 6 , wherein the line interleaving controller generates and outputs the virtual data lines such that the number of the virtual data lines is equal to a greater one of a first pipeline delay size and a second pipeline delay size, the first pipeline delay size corresponding to a sum of the module delay sizes of the delayed processing modules included in the first pipeline circuit, the second pipeline delay size corresponding to a sum of the module delay sizes of the delayed processing modules included in the second pipeline circuit.

8. The image signal processor of claim 6 , wherein the image signal processor core further includes:
a mixer configured to mix outputs of the first pipeline circuit and the second pipeline circuit.

9. The image signal processor of claim 8 , wherein one of the first pipeline circuit and the second pipeline circuit includes:
a delay buffer configured to delay received data lines without processing such that the first pipeline delay size and the second pipeline delay size becomes equal to each other.

10. The image signal processor of claim 1 , wherein the line interleaving controller receives a plurality of first image data lines included in a first image frame through a first channel and a plurality of second image data lines included in a second image frame through a second channel, generate one or more first virtual data lines corresponding to the first image frame and one or more second virtual data lines corresponding to the second image frame, and transfer the plurality of first image data lines, the plurality of second image data lines, the first virtual data lines and the second virtual data lines sequentially line by line with a time-division multiplexing (TDM) scheme to the image signal processor core.

11. The image signal processor of claim 10 , wherein the line interleaving controller transfers, as an input stream signal to the image signal processor core, the plurality of first image data lines, the plurality of second image data lines, the first virtual data lines and the second virtual data lines.

12. The image signal processor of claim 11 , wherein the line interleaving controller transfers the input stream signal to the image signal processor core while the image signal processor core processes the end image data lines of the first image frame or the second image frame.

13. The image signal processor of claim 11 , wherein the line interleaving controller generates a channel identification signal indicating whether a present data in the input stream signal corresponds to the first image frame or the second image frame, and
wherein the image signal processor core performs independently processing of the first image frame and processing of the second image frame based on the channel identification signal.

14. The image signal processor of claim 11 , wherein the line interleaving controller generates a virtual line identification signal indicating whether a present data line in the input stream signal correspond to the image data line or the virtual data line, and
wherein the image signal processor core performs processing of the end image data lines of the first image frame and the second image frame based on the virtual line identification signal.

15. The image signal processor of claim 11 , wherein the line interleaving controller includes:
a buffer circuit configured to buffer the plurality of the first image data lines and the plurality of the second image data lines to selectively output each first image data line or each second image data line;
a virtual line generator configured to generate the first virtual data lines and the second virtual data lines and selectively output the first virtual data line or the second virtual data line;
a multiplexer configured to output the input stream signal by selecting an output of the buffer circuit and an output of the virtual line generator; and
a control logic circuit configured to control operations of the buffer circuit, the virtual line generator and the multiplexer.

16. The image signal processor of claim 15 , wherein the buffer circuit includes:
a common memory region configured to store the first image data lines and the second image data lines according to an reception order that the buffer circuit receives the first image data lines and the second image data lines, and
wherein the control logic circuit configured to control the buffer circuit such that the buffer circuit outputs, according to the reception order, the first image data lines and the second image data lines stored in the common memory region.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cha Kilhyung
• Park Jinsoo
• Lee Dongwoo
• Lee Serhoon
• Huh Sungjin

Classifications

• H04N23/84

  for processing colour signals · CPC title

• H04N23/81

  for suppressing or minimising disturbance in the image signal generation · CPC title

• H04N23/80

  Camera processing pipelines; Components thereof · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title