Arbitration scheme for coherent and non-coherent memory requests

Patent metadata

Field	Value
Publication number	US-11513973-B2
Application number	US-201916723185-A
Country	US
Kind code	B2
Filing date	Dec 20, 2019
Priority date	Dec 20, 2019
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

A processor in a system is responsive to a coherent memory request buffer having a plurality of entries to store coherent memory requests from a client module and a non-coherent memory request buffer having a plurality of entries to store non-coherent memory requests from the client module. The client module buffers coherent and non-coherent memory requests and releases the memory requests based on one or more conditions of the processor or one of its caches. The memory requests are released to a central data fabric and into the system based on a first watermark associated with the coherent memory buffer and a second watermark associated with the non-coherent memory buffer.

First claim

What is claimed is:

1. A processor comprising:
client module circuitry;
a coherent memory request buffer having a plurality of entries to store coherent memory requests; and
a non-coherent memory request buffer having a plurality of entries to store non-coherent memory requests;
wherein the client module circuitry is configured to:
buffer coherent memory requests in the coherent memory request buffer, and release a plurality of buffered coherent memory requests for processing when a quantity of the buffered coherent memory requests exceeds a first memory request threshold; and
buffer non-coherent memory requests in the non-coherent memory request buffer, and release the buffered non-coherent memory requests for processing when a quantity of the buffered non-coherent memory requests exceeds a second memory request threshold, wherein the first memory request threshold is different from the second memory request threshold.

2. The processor of claim 1 , wherein the client module circuitry is further configured to:
receive an indication that a processor core of the processor is in a specified power state; and
begin to buffer the coherent memory requests and buffer the non-coherent memory requests based on the received indication.

3. The processor of claim 1 , further comprising:
a memory manager for translating client virtual memory addresses of at least one of the coherent memory requests and the non-coherent memory requests into physical client memory addresses of the client module circuitry.

4. The processor of claim 1 , wherein:
the non-coherent memory requests include non-coherent prefetch memory requests.

5. The processor of claim 1 , wherein:
each of the non-coherent memory requests is to be translated based on a first memory address translation and a second memory address translation associated with a virtualization based security (VBS) mechanism.

6. The processor of claim 1 , wherein the client module circuitry is further configured to:
release the plurality of the requests when at least one of:
a first number of buffered coherent memory requests in the coherent memory request buffer exceeds the first memory request threshold; and
a second number of buffered non-coherent memory requests in the non-coherent memory request buffer exceeds the second memory request threshold after receiving a signal that a processor core of the processor is in a low power state.

7. The processor of claim 1 , wherein the client module circuitry is further configured to:
limit a number of coherent memory requests released from the coherent memory request buffer based on an amount of coherent memory request activity.

8. A system comprising:
client module circuitry;
a coherent memory request buffer having a plurality of entries to store coherent memory requests from the client module circuitry;
a non-coherent memory request buffer having a plurality of entries to store non-coherent memory requests from the client module circuitry;
wherein the client module circuitry is configured to:
buffer coherent memory requests in the coherent memory request buffer, and release a plurality of buffered coherent memory requests for processing when a quantity of the buffered coherent memory requests exceeds a first memory request threshold; and
buffer non-coherent memory requests in the non-coherent memory request buffer and release the buffered non-coherent memory requests for processing when a quantity of the buffered non-coherent memory requests exceeds a second memory request threshold that is different from the first memory request threshold.

9. The system of claim 8 , wherein the client module circuitry is further configured to:
begin to buffer the coherent memory requests and buffer the non-coherent memory requests in response to a signal indicating that a processor core in the system is in a low power state.

10. The system of claim 8 , wherein:
each of the non-coherent memory requests includes at least one of a non-coherent prefetch memory request and a demand non-coherent memory request.

11. The system of claim 8 , wherein:
the client module circuitry is configured to process each of the non-coherent memory requests using a first memory address translation and a second memory address translation consistent with a virtualization based security (VBS) mechanism.

12. The system of claim 8 , further comprising:
second client module circuitry, a second coherent memory request buffer associated with the second client module circuitry, and a second non-coherent memory request buffer associated with the second client module circuitry.

13. The system of claim 8 , wherein the release of the coherent memory requests and of the non-coherent memory requests is initiated in response to receiving a release signal that is generated based on at least one of:
a first number of buffered coherent memory requests in the coherent memory request buffer exceeding the first memory request threshold; and/or
a second number of buffered non-coherent memory requests in the non-coherent memory request buffer exceeding the second memory request threshold after receiving a signal that a processor core of the system is in a low power state.

14. The system of claim 8 , wherein the client module circuitry is further configured to:
detect an amount of coherent memory request activity in the system; and
limit a number of coherent memory requests released from the coherent memory request buffer based on the detected amount of coherent memory request activity.

15. A method for arbitrating device generated coherent and non- coherent memory requests, the method comprising:
detecting a power state of a processor core and a processor shared cache; and
in response to detecting a low-power state of the processor core:
buffering coherent memory requests in a coherent memory request buffer;
buffering non-coherent memory requests in a non-coherent memory request buffer;
releasing coherent memory requests in the coherent memory request buffer based on a quantity of the coherent memory requests exceeding a first memory request threshold; and
releasing non-coherent memory requests in the non-coherent memory request buffer based on a quantity of the non-coherent memory requests exceeding a second memory request threshold that is different from the first memory request threshold.

16. The method of claim 15 , wherein:
releasing the one or more non-coherent memory requests and the one or more coherent memory requests includes releasing the memory requests as a batch based on the low-power state.

17. The method of claim 15 , wherein:
each of the non-coherent memory requests includes at least one of a non-coherent prefetch memory request and a demand non-coherent memory request.

18. The method of claim 15 , further comprising:
performing a first memory address translation and a second memory address translation consistent with a virtualization based security (VBS) mechanism for each of the non-coherent memory requests after releasing the one or more non-coherent memory requests.

19. The method of claim 15 , wherein releasing the non-coherent memory requests and the coherent memory requests is based on at least one of:
detecting a first number of buffered coherent memory requests in the coherent memory request buffer exceeding the first memory request threshold; and
detecting a second number of buffered non-coherent memory requests in the non-coherent memory request buffer exceeding the second memory request threshold after receiving a signal that the

Assignees

• Advanced Micro Devices Inc

Inventors

• Arora Sonu
• Tsien Benjamin
• Branover Alexander J

Classifications

• G06F11/3062

  where the monitored property is the power consumption (power management in a computing system G06F1/3203) · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F9/30047

  Prefetch instructions; cache control instructions · CPC title

• G06F9/5022

  Mechanisms to release resources · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title