Data transferring apparatus and method for transferring data with overlap

Patent metadata

Field	Value
Publication number	US-11513852-B2
Application number	US-202016874692-A
Country	US
Kind code	B2
Filing date	May 15, 2020
Priority date	Feb 27, 2020
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

A data transferring apparatus and a method for transferring data with overlap are provided. The data transferring apparatus includes a command splitter circuit and a plurality of tile processing circuits. The command splitter circuit splits a block level transfer command into a plurality of tile transfer tasks. The command splitter circuit may issue the tile transfer tasks to the tile processing circuits in a plurality of batches. The tile processing circuits may execute the tile transfer tasks in a current batch, so as to read data of a plurality of corresponding tiles among a plurality of source tiles of a source block to the tile processing circuits. After all the tile transfer tasks in the current batch have been executed by the tile processing circuits, the command splitter circuit issues the tile transfer tasks in a next batch of the batches to the tile processing circuits.

First claim

What is claimed is:

1. A data transferring apparatus, configured to transfer data with overlap, comprising:
a command splitter circuit, configured to receive a block level transfer command, split the block level transfer command into a plurality of tile transfer tasks, split the tile transfer tasks into a plurality of batches, and issue the tile transfer tasks in a current batch of the batches; and
a plurality of tile processing circuits, configured to execute the tile transfer tasks in the current batch, so as to read data of a plurality of first corresponding tiles among a plurality of source tiles of a source block to the tile processing circuits as a plurality of cache tile data, wherein after the tile transfer tasks in the current batch have been executed by the tile processing circuits, the command splitter circuit issues the tile transfer tasks in a next batch of the batches to the tile processing circuits;
wherein the tile processing circuits are split into a plurality of groups and each of the groups further comprises:
a synchronization circuit, coupled to the tile processing circuits belonging to the group, wherein after the tile processing circuits belonging to the group have completed corresponding tile transfer tasks in the current batch, the synchronization circuit feeds back a batch completion signal to the command splitter circuit, wherein
only when all synchronization circuits in the groups feed back the batch completion signal to the command splitter circuit, the command splitter circuit issues the tile transfer tasks in the next batch to the tile processing circuits.

2. The data transferring apparatus according to claim 1 , wherein when the tile transfer tasks in the next batch are issued to the tile processing circuits, the tile processing circuits write the cache tile data to a destination block, and then the tile processing circuits execute the tile transfer tasks in the next batch, so as to read data of a plurality of second corresponding tiles of the source block to the tile processing circuits.

3. The data transferring apparatus according to claim 2 , wherein the source block is partially overlapped with the destination block.

4. The data transferring apparatus according to claim 2 , wherein the source block and the destination block are stored in a memory.

5. The data transferring apparatus according to claim 2 , wherein
when an address of the source block is prior to an address of the destination block, an address of the tile transfer tasks in the current batch is posterior to an address of the tile transfer tasks in the next batch; and
when the address of the source block is posterior to the address of the destination block, the address of the tile transfer tasks in the current batch is prior to the address of the tile transfer tasks in the next batch.

6. The data transferring apparatus according to claim 2 , wherein
in an address space, when a first row address of the source block is prior to a first row address of the destination block, the command splitter circuit issues the batches in an order of “from a next row to a previous row”; and
in the address space, when the first row address of the source block is posterior to the first row address of the destination block, the command splitter circuit issues the batches in an order of “from a previous row to a next row”.

7. The data transferring apparatus according to claim 1 , wherein the source tiles are split into a plurality of source rows in an address space and the tile transfer tasks in the current batch correspond to at least one row in the source rows.

8. The data transferring apparatus according to claim 1 , wherein each of the tile processing circuits comprises:
a buffer;
a tile processing unit, coupled to the command splitter circuit to receive a plurality of corresponding tile transfer tasks in the current batch and configured to issue a plurality of tile configuration requests to the buffer based on the corresponding tile transfer tasks; and
a cache circuit, coupled to the buffer and configured to execute the tile configuration requests, so as to read data of a plurality of corresponding tiles in the source block to the cache circuit.

9. The data transferring apparatus according to claim 8 , wherein when the tile transfer tasks in the next batch are issued to the tile processing circuits, the cache circuit writes data to a destination block, and then the cache circuit executes the tile configuration requests corresponding to the next batch.

10. A method for transferring data with overlap, comprising:
receiving, by a command splitter circuit, a block level transfer command;
splitting, by the command splitter circuit, the block level transfer command into a plurality of tile transfer tasks, and splitting the tile transfer tasks into a plurality of batches;
issuing the tile transfer tasks in a current batch of the batches;
executing, by a plurality of tile processing circuits, the tile transfer tasks in the current batch, so as to read data of a plurality of first corresponding tiles among a plurality of source tiles of a source block to the tile processing circuits as a plurality of cache tile data; and
issuing, by the command splitter circuit, the tile transfer tasks in a next batch of the batches to the tile processing circuits after the tile transfer tasks in the current batch have been executed by the tile processing circuits;
wherein the plurality of tile processing circuits are split into a plurality of groups and each of the groups further comprises:
a synchronization circuit, coupled to the tile processing circuits belonging to the group, wherein after the tile processing circuits belonging to the group have completed corresponding tile transfer tasks in the current batch, the synchronization circuit feeds back a batch completion signal to the command splitter circuit, wherein
only when all synchronization circuits in the groups feed back the batch completion signal to the command splitter circuit, the command splitter circuit issues the tile transfer tasks in the next batch to the tile processing circuits.

11. The method for transferring data according to claim 10 , further comprising:
writing the cache tile data to a destination block when the tile transfer tasks in the next batch are issued to the tile processing circuits, and then executing the tile transfer tasks in the next batch, so as to read data of a plurality of second corresponding tiles of the source block to the tile processing circuits.

12. The method for transferring data according to claim 11 , wherein the source block is partially overlapped with the destination block.

13. The method for transferring data according to claim 11 , wherein the source block and the destination block are stored in a memory.

14. The method for transferring data according to claim 11 , wherein
when an address of the source block is prior to an address of the destination block, an address of the tile transfer tasks in the current batch is posterior to an address of the tile transfer tasks in the next batch; and
when the address of the source block is posterior to the address of the destination block, the address of the tile transfer tasks in the current batch is prior to the address of the tile transfer tasks in the next batch.

15. The method for transferring data according to claim 11 , further comprising:
issuing the batches in an order of “from a next row to a previous row” in an address space when a first row address of the source block is prior to a first row address of the destination block; and
issuing the batches in an order of “from a previous

Assignees

• Glenfly Tech Co Ltd

Inventors

• Que Heng
• Wang Yuanfeng
• Gu Deming
• Wu Fengxia

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F9/5027 Primary

  the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title

• G06F3/0647 Primary

  Migration mechanisms · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F9/5005 Primary

  to service a request · CPC title