System and method for caching data in persistent memory of a non-volatile memory express storage array enclosure

Patent metadata

Field	Value
Publication number	US-11513699-B2
Application number	US-201916529361-A
Country	US
Kind code	B2
Filing date	Aug 1, 2019
Priority date	Aug 1, 2019
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

A method, computer program product, and computing system for receiving, via a storage processor of a storage system, a write request for writing a data portion to a storage array enclosure of non-volatile memory express (NVMe) drives communicatively coupled to the storage processor, where the write request may be received from a host. The data portion may be written to a persistent memory write cache within the storage array enclosure.

First claim

What is claimed is:

1. A computer-implemented method comprising:
receiving, via a first storage processor or a second storage processor of a storage system, a write request for writing a data portion to a storage array enclosure of non-volatile memory express (NVMe) drives communicatively coupled to and physically separated in a different enclosure from the first storage processor or the second storage processor, wherein the write request is received from a host, wherein the first storage processor and the second storage processor are communicatively coupled to the storage array enclosure of NVMe devices via non-volatile memory express over fabrics (NVMe-oF), wherein the storage array enclosure further includes a first storage controller, a second storage controller, a drive carrier, a disk drive, and a midplane, wherein the midplane is configured to distribute power and signals to components within the storage array enclosure, wherein each of the NVMe devices is coupled directly to the first storage controller and the second storage controller, wherein the first storage controller and second storage controller each include a module configured to support, control, and monitor the storage array enclosure;
writing the data portion to a persistent memory write cache within the storage array enclosure, wherein writing the data portion to the persistent memory write cache includes:
providing the write request to a first persistent memory device of the persistent memory write cache via a first remote direct memory access (RDMA) write operation from the first storage processor directly to the first persistent memory device of the persistent memory write cache;
providing the write request to a second persistent memory device of the persistent memory write cache via a second RDMA write operation from the second storage processor directly to the second persistent memory device of the persistent memory write cache; and
in response to the first storage controller receiving a write request, multicasting the write request from the first storage controller to the second storage controller, wherein the first storage controller and the second storage controller are communicatively coupled;

generating, in response to writing the data to the persistent memory write cache within the storage array enclosure, a write notification to the host that provided the write request;
determining whether the first storage processor is unavailable;
in response to determining the first storage processor is unavailable, accessing write cache data associated with the first storage processor through the second storage processor, the first storage controller, and the second storage controller, wherein accessing write cache data associated with the first storage processor occurs from the second persistent memory device; and
in response to determining the first storage processor is unavailable, continuing to replicate the data portion of the write request to the first persistent memory device and the second persistent memory device, via the second storage processor.

2. The computer implemented method of claim 1 , wherein the storage system includes a plurality of storage processors configured to receive a plurality of write requests.

3. The computer implemented method of claim 2 , further comprising:
accessing, via a first storage processor, write cache data associated with a second storage processor from the persistent memory write cache within the storage array enclosure.

4. A computer program product residing on a non-transitory computer readable medium having a plurality of instructions stored thereon which, when executed by a processor, cause the processor to perform operations comprising:
receiving, via a first storage processor or a second storage processor of a storage system, a write request for writing a data portion to a storage array enclosure of non-volatile memory express (NVMe) drives communicatively coupled to and physically separated in a different enclosure from the first storage processor or the second storage processor, wherein the write request is received from a host, wherein the first storage processor and the second storage processor are communicatively coupled to the storage array enclosure of NVMe devices via non-volatile memory express over fabrics (NVMe-oF), wherein the storage array enclosure further includes a first storage controller, a second storage controller, a drive carrier, a disk drive, and a midplane, wherein the midplane is configured to distribute power and signals to components within the storage array enclosure, wherein each of the NVMe devices is coupled directly to the first storage controller and the second storage controller, wherein the first storage controller and second storage controller each include a module configured to support, control, and monitor the storage array enclosure;
writing the data portion to a persistent memory write cache within the storage array enclosure, wherein writing the data portion to the persistent memory write cache includes:
providing the write request to a first persistent memory device of the persistent memory write cache via a first remote direct memory access (RDMA) write operation from the first storage processor directly to the first persistent memory device of the persistent memory write cache;
providing the write request to a second persistent memory device of the persistent memory write cache via a second RDMA write operation from the second storage processor directly to the second persistent memory device of the persistent memory write cache; and
in response to the first storage controller receiving a write request, multicasting the write request from the first storage controller to the second storage controller, wherein the first storage controller and the second storage controller are communicatively coupled;

generating, in response to writing the data to the persistent memory write cache within the storage array enclosure, a write notification to the host that provided the write request;
determining whether the first storage processor is unavailable;
in response to determining the first storage processor is unavailable, accessing write cache data associated with the first storage processor through the second storage processor, the first storage controller, and the second storage controller, wherein accessing write cache data associated with the first storage processor occurs from the second persistent memory device; and
in response to determining the first storage processor is unavailable, continuing to replicate the data portion of the write request to the first persistent memory device and the second persistent memory device, via the second storage processor.

5. The computer program product of claim 4 , wherein the storage system includes a plurality of storage processors configured to receive a plurality of write requests.

6. The computer program product of claim 5 , further comprising instructions for:
accessing, via a first storage processor, write cache data associated with a second storage processor from the persistent memory write cache within the storage array enclosure.

7. A computing system including a processor and memory configured to perform operations comprising:
receiving, via a first storage processor or a second storage processor of a storage system, a write request for writing a data portion to a storage array enclosure of non-volatile memory express (NVMe) drives communicatively coupled to and physically separated in a different enclosure from the first storage processor or the second storage processor, wherein the write request is received from a host, wherein the first storage processor and the second storage processor are communicatively coupled to the storage array enclosure of NVMe devices v

Assignees

• Emc Ip Holding Co Llc
• EMP IP Holding Company LLC

Inventors

• O'Brien Iii Walter A
• Dibb Thomas N
• Shain Randall H

Classifications

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F2212/313

  In storage device · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F2212/286

  Mirrored cache memory · CPC title

• G06F3/0626 Primary

  Reducing size or complexity of storage systems · CPC title