Power management for a graphics processing unit or other circuit

Patent metadata

Field	Value
Publication number	US-11513585-B1
Application number	US-202117221076-A
Country	US
Kind code	B1
Filing date	Apr 2, 2021
Priority date	Apr 20, 2011
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

In one embodiment, a system includes power management control that controls a duty cycle of a processor to manage power. The duty cycle may be the amount of time that the processor is powered on as a percentage of the total time. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. For example, the processor may be a graphics processing unit (GPU), and the period of time over which the duty cycle is managed may be a frame to be displayed on the display screen viewed by a user of the system.

First claim

What is claimed is:

1. An integrated circuit comprising:
a processor;
a power monitor coupled to the processor and configured to generate a power measurement representing power consumed in the processor;
a controller coupled to the power monitor and the processor, wherein:
the controller is configured to limit a first amount of time within a given fixed time period that the processor is powered on to no more than a first limit amount,
the first limit amount is determined at a current operating point of the processor to reduce an error between a target power measurement and the power measurement generated by the power monitor,
the given fixed time period is one of a plurality of fixed time periods over which the processor operates, wherein the processor performs a task within each of the plurality of fixed time periods during use, and
the controller is configured to control the current operating point of the processor based on the first amount of time; and

a plurality of temperature sensors configured to measure a plurality of temperatures, wherein the target power measurement is generated based on the plurality of temperatures.

2. The integrated circuit as recited in claim 1 further comprising a temperature controller coupled to the plurality of temperature sensors and configured to generate the target power measurement based on the plurality of temperatures.

3. The integrated circuit as recited in claim 2 wherein the temperature controller implements at least one of proportional control, integral control, or derivative control.

4. The integrated circuit as recited in claim 1 wherein the plurality of temperature sensors are physically distributed over a surface of the integrated circuit.

5. The integrated circuit as recited in claim 1 wherein the current operating point comprises an operating voltage and an operating frequency of the processor.

6. The integrated circuit as recited in claim 1 wherein the controller is configured to:
detect that the first amount of time is less than a first threshold; and
reduce the current operating point based on detecting that the first amount of time is less than the first threshold.

7. The integrated circuit as recited in claim 6 wherein the controller is configured to:
detect that the first amount of time is greater than a second threshold and that the first limit amount is at a maximum; and
increase the current operating point based on detecting that the first amount of time is greater than the second threshold and that the first limit amount is at the maximum.

8. The integrated circuit as recited in claim 1 wherein the controller comprises a second processor and a non-transitory computer accessible storage medium storing a plurality of instructions which, when executed by the second processor, causes the second processor to perform operations comprising at least a portion of operations performed by the controller during use.

9. The integrated circuit as recited in claim 8 wherein the controller further comprises hardware circuitry configured to perform a remaining portion of operations performed by the controller during use.

10. The integrated circuit as recited in claim 1 wherein the controller is configured to power off the processor in the given fixed time period based on completion of the task even if the first limit amount has not been exhausted.

11. The integrated circuit as recited in claim 1 wherein the power monitor is configured to estimate the power measurement based on activity in the processor.

12. The integrated circuit as recited in claim 1 wherein the power monitor is configured to measure power consumption from a power supply to the processor to determine the power measurement.

13. An integrated circuit comprising:
a processor;
a power monitor coupled to the processor and configured to generate a power measurement representing power consumed in the processor;
a controller coupled to the power monitor and the processor, wherein:
the controller is configured to limit a first amount of time within a given fixed time period that the processor is powered on to no more than a first limit amount,
the first limit amount is determined at a current operating point of the processor to reduce an error between a target power measurement and the power measurement generated by the power monitor,
the given fixed time period is one of a plurality of fixed time periods over which the processor operates, wherein the processor performs a task within each of the plurality of fixed time periods during use, and
the controller is configured to permit the processor to exceed the first limit amount subsequent to one or more of the plurality of fixed time periods in which the processor completed the task in less than the first limit amount.

14. The integrated circuit as recited in claim 13 wherein the controller comprises an integral controller, and wherein an amount of time not consumed by the processor in the one or more of the plurality of fixed time periods is accumulated in the integral controller.

15. The integrated circuit as recited in claim 13 further comprising a plurality of temperature sensors configured to measure a plurality of temperatures, wherein the target power measurement is generated based on the plurality of temperatures.

16. The integrated circuit as recited in claim 15 further comprising a temperature controller coupled to the plurality of temperatures sensors and configured to generate the target power measurement based on the plurality of temperatures.

17. The integrated circuit as recited in claim 16 wherein the temperature controller implements at least one of proportional control, integral control, or derivative control.

18. The integrated circuit as recited in claim 15 wherein the plurality of temperature sensors are physically distributed over a surface of the integrated circuit.

19. A method comprising:
generating a power measurement representing power consumed in a processor;
limiting a first amount of time within a given fixed time period that the processor is powered on to no more than a first limit amount, wherein the first limit amount is determined at a current operating point of the processor to reduce an error between a target power measurement and the power measurement from the generating step, and wherein the given fixed time period is one of a plurality of fixed time periods over which the processor operates, wherein the processor performs a task within each of the plurality of fixed time periods during use;
controlling the current operating point of the processor based on the first amount of time; and
measuring a plurality of temperatures in a plurality of temperature sensors, wherein the target power measurement is generated based on the plurality of temperatures.

20. The method as recited in claim 19 further comprising permitting the processor to exceed the first limit amount subsequent to one or more of the plurality of fixed time periods in which the processor completed the task in less than the first limit amount.

Assignees

• Apple Inc

Inventors

• Law Patrick Y
• Drebin Robert A
• Cox Keith
• Ismail James S

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F1/3218

  of display devices · CPC title

• G06F1/3265 Primary

  Power saving in display device · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title