Logic circuitry package

US11511546B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11511546-B2
Application numberUS-201916768228-A
CountryUS
Kind codeB2
Filing dateOct 25, 2019
Priority dateDec 3, 2018
Publication dateNov 29, 2022
Grant dateNov 29, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A logic circuitry package for a replaceable print apparatus component includes an interface to communicate with a print apparatus logic circuit, and at least one logic circuit to transmit, via the interface, a sensor ID parameter and a limit parameter, the sensor ID parameter indicating a first sensor ID. The logic circuit is to receive, via the interface, a first request corresponding to the first sensor ID with the component connected to the apparatus and the apparatus not pneumatically actuating the component. The logic circuit is to transmit, via the interface, a first digital value in response to the first request. The logic circuit is to receive, via the interface, a second request corresponding to the first sensor ID with the component connected to the apparatus and the apparatus pneumatically actuating the component. The logic circuit is to transmit, via the interface, a second digital value in response to the second request. A difference between the first digital value and the second digital value is greater than the limit parameter.

First claim

Opening claim text (preview).

The invention claimed is: 1. A logic circuitry package for a replaceable print apparatus component comprising an interface to communicate with a print apparatus logic circuit, and at least one logic circuit configured to: transmit, via the interface, a sensor ID parameter and a limit parameter, the sensor ID parameter indicating a first sensor ID; receive, via the interface, a first request corresponding to the first sensor ID with the component connected to the apparatus and the apparatus not pneumatically actuating the component; transmit, via the interface, a first digital value in response to the first request; receive, via the interface, a second request corresponding to the first sensor ID with the component connected to the apparatus and the apparatus pneumatically actuating the component; and transmit, via the interface, a second digital value in response to the second request, wherein a difference between the first digital value and the second digital value is greater than the limit parameter. 2. The logic circuitry package of claim 1 , wherein the at least one logic circuit is configured to: receive, via the interface, a first calibration parameter; and transmit the first digital value in response to the first request and the second digital value in response to the second request. 3. The logic circuitry package of claim 2 , wherein the at least one logic circuit is configured to: receive, via the interface, different calibration parameters including the first calibration parameter; and transmit the first digital value in response to the first calibration parameter. 4. The logic circuitry package of claim 3 , wherein the at least one logic circuit is configured to: transmit different digital values in response to the respective different calibration parameters. 5. The logic circuitry package of claim 4 , wherein the different digital values include the first digital value and at least one different digital value clipped at the end of a range defined by a natural number of bytes. 6. The logic circuitry package of claim 1 , wherein the at least one logic circuit is configured to transmit the sensor ID parameter and the limit parameter in response to a request to a first default address of the logic circuitry package and to transmit the first and second digital values in response to the first and second requests to a second default address and/or a reconfigured address of the logic circuitry package. 7. The logic circuitry package of claim 1 , wherein the at least one logic circuit is configured to: identify a plurality of different sensor IDs; and upon receiving a request corresponding to one of the plurality of sensor IDs, transmit, via the interface, a digital value in response to the request based on a sensor signal from one of the following: a single sensor for the plurality of sensor IDs, or a respective sensor cell of a plurality of sensor cells where each sensor cell of the plurality of sensor cells corresponds to a respective sensor ID of the plurality of sensor IDs. 8. The logic circuitry package of claim 1 , wherein the at least one logic circuit is configured to: receive, via the interface, a third request corresponding to the first sensor ID with the component connected to the apparatus and the apparatus not pneumatically actuating the component; and transmit, via the interface, a third digital value in response to the third request, wherein a difference between the first digital value and the third digital value is less than or equal to the limit parameter. 9. The logic circuitry package of claim 8 , wherein the at least one logic circuit is configured to, with the logic circuitry package mounted to the component and with the component connected to the apparatus and the apparatus not pneumatically actuating the component, output the first and/or third digital value at an internal reservoir pressure of the component of approximately 0 kPa gauge pressure or less. 10. The logic circuitry package of claim 1 , wherein the at least one logic circuit comprises a memory storing the sensor ID parameter and the limit parameter, wherein the memory stores digitally signed data comprising the sensor ID parameter and the limit parameter. 11. The logic circuitry package of claim 1 , wherein the at least one logic circuit is configured to: receive, via the interface, a fourth request corresponding to a second sensor ID with the component connected to the apparatus and the apparatus not pneumatically actuating the component; transmit, via the interface, a resting state digital value in response to the fourth request; receive, via the interface, a fifth request corresponding to the second sensor ID with the component connected to the apparatus and the apparatus pneumatically actuating the component; and transmit, via the interface, a fifth digital value in response to the fifth request, wherein a difference between the resting state digital value and the fifth digital value is greater than the limit parameter. 12. The logic circuitry package of claim 2 , wherein the at least one logic circuit is configured to: receive, via the interface, the first calibration parameter; and transmit the resting state digital value in response to the fourth request and the fifth digital value in response to the fifth request. 13. The logic circuitry package of claim 1 , wherein the at least one logic circuit comprises a memory storing the sensor ID parameter, a step parameter, and a step number parameter, and the at least one logic circuit is configured to: transmit, via the interface, the sensor ID parameter, the step parameter, and the step number parameter to instruct the print apparatus logic circuit which further sensor IDs to address in further requests based on the stored sensor ID parameter, the step parameter, and the step number parameter whereby the step number parameter corresponds to a number of different sensor IDs and the step parameter corresponds to the step between subsequent sensor IDs; receive, via the interface, first further requests corresponding to the different sensor IDs with the component connected to the apparatus and the apparatus not pneumatically actuating the component; transmit, via the interface, respective resting state digital values in response to the first further requests; receive, via the interface, second further requests corresponding to the different sensor IDs with the component connected to the apparatus and the apparatus pneumatically actuating the component; and transmit, via the interface, digital values in response to the second further requests wherein for the majority of the digital values a difference between the digital value and the corresponding resting state digital value is greater than the limit parameter. 14. The logic circuitry package of claim 13 , wherein the at least one logic circuit is configured to: receive, via the interface, third further requests corresponding to the different sensor IDs with the component connected to the apparatus and the apparatus not pneumatically actuating the component; and transmit, via the interface, further digital values in response to the third further requests wherein for the majority of these further digital values a difference between the further digital value and the corresponding resting state digital value is less than or equal to the limit parameter. 15. The logic circuitry package of claim 14 , wherein the at least one logic circuit comprises a memory storing the sensor ID parameter, the limit parameter, the step parameter, and a step number parameter. 16. The logic c

Assignees

Inventors

Classifications

  • electronically · CPC title

  • Apparatus for additive manufacturing; Details thereof or accessories therefor · CPC title

  • Outer structure · CPC title

  • Multiplexing · CPC title

  • for discrete levels · CPC title

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Frequently asked questions

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What does patent US11511546B2 cover?
A logic circuitry package for a replaceable print apparatus component includes an interface to communicate with a print apparatus logic circuit, and at least one logic circuit to transmit, via the interface, a sensor ID parameter and a limit parameter, the sensor ID parameter indicating a first sensor ID. The logic circuit is to receive, via the interface, a first request corresponding to the f…
Who is the assignee on this patent?
Hewlett Packard Development Co
What technology area does this patent fall under?
Primary CPC classification B41J2/17546. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Nov 29 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).