Large-format battery management system with in-rush current protection for master-slave battery packs

US11509144B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11509144-B2
Application numberUS-202117549398-A
CountryUS
Kind codeB2
Filing dateDec 13, 2021
Priority dateJun 2, 2020
Publication dateNov 22, 2022
Grant dateNov 22, 2022

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  1. Title

    What the patent document calls the invention.

  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A system for suppressing inrush currents is described. The system may include a negative temperature coefficient (NTC) thermistor and a positive temperature coefficient (PTC) thermistor arranged in series between a power source and a battery system to be charged. At a low temperature, while the PTC thermistor provides only minimal resistance to minimize an inrush current, the NTC thermistor provides increased resistance. As the temperature increases, the resistance provided by the PTC thermistor increases as the resistance from the NTC thermistor decreases. The system may be used in conjunction with a battery charging system has at least one current pathway from the power source to the battery system.

First claim

Opening claim text (preview).

What is claimed is: 1. A system for powering a load comprising: a first switch having a first terminal, a second terminal, and first control terminal; one or more first thermistors of a first type of thermistor and is electrically connected to the second terminal of the first switch; one or more second thermistors of a second type of thermistor; and a second switch having a third terminal, a fourth terminal, and a second control terminal, wherein a first resistance of the first type of thermistor responds, to a change in temperature, in an opposite direction than how a second resistance of the second thermistor responds to the change in temperature, wherein the first terminal is configured to be electrically connected to a power source, wherein the one or more second thermistors are configured to be electrically connected to the load, wherein the one or more second thermistors are in series with the one or more first thermistors, wherein the third terminal is configured to be electrically connected to the power source the fourth terminal is configured to be electrically connected to the load, wherein the microprocessor is configured to provide a second signal to the second control terminal of the second switch, wherein, during a first time interval, the microprocessor: controls the first switch to permit conduction of power between the first terminal and the second terminal, and controls the second switch to prevent conduction of power between the third terminal and the fourth terminal, wherein, during a second time interval, the microprocessor: controls the first switch to prevent conduction of power between the first terminal and the second terminal, and controls the second switch to permit conduction of power between the third terminal and the fourth terminal, wherein, at a beginning of the first time interval, one of the first or second type of thermistor has a greater resistance than a corresponding second or first type of thermistor, and wherein, at the end of the first time interval, the one of the first or second type of thermistor has a lower resistance than the corresponding second or first type of thermistor. 2. The system of claim 1 , wherein the first type of thermistor is a positive temperature control (PTC) thermistor, wherein the second type of thermistor is a negative temperature control (NTC) thermistor. 3. The system of claim 1 , further comprising: a resistor electrically connected between the one or more second thermistors and the load. 4. The system of claim 1 , further comprising: a third switch having a third terminal, a fourth terminal, and a second control terminal, wherein the third terminal is connected to the one or more second thermistors, and wherein the fourth terminal is configured to be electrically connected to the load. 5. The system of claim 1 , further comprising: a microprocessor configured to provide a signal to the first control terminal of the first switch. 6. The system of claim 1 , further comprising: a resistor electrically connected between the fourth terminal and the load. 7. The system of claim 1 , further comprising: a third switch comprising a fifth terminal, a sixth terminal, and a third control terminal, wherein the fifth terminal is connected to the fourth terminal, and wherein the sixth terminal is configured to be electrically connected to the load. 8. The system of claim 5 , wherein, during a charging time interval, the microprocessor controls the first switch to permit conduction of power between the first terminal and the second terminal, and wherein, during another time interval, the microprocessor controls the first switch to prevent conduction of power between the first terminal and the second terminal. 9. The system of claim 1 , wherein, for a range of temperatures, a series resistance of a combination of the one or more first thermistors and one or more second thermistors is lower than the series resistance of the combination below the range of temperatures. 10. The system of claim 1 , wherein, for a range of temperatures, a series resistance of a combination of the one or more first thermistors and one or more second thermistors is lower than the series resistance of the combination above the range of temperatures. 11. The system of claim 1 , wherein the first switch comprises a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), or a power MOSFET. 12. The system of claim 1 , wherein the one or more first thermistors comprise two or more thermistors in series or parallel. 13. The system of claim 1 , wherein the one or more first thermistors comprise PTC thermistors or NTC thermistors. 14. The system of claim 1 , wherein the one or more first thermistors comprise at least one thermistor of the first type in series with a parallel combination of two or more thermistors of the first type, and wherein the one or more first thermistors comprise PTC thermistors or NTC thermistors. 15. A method comprising: providing a first switch; providing a second switch; providing a positive temperature control (PTC) thermistor in series with a negative temperature control (NTC) thermistor; and controlling the first switch to permit, at a first time, current to flow from a power source to a load via the first switch and via a series connection of a positive temperature control (PTC) thermistor and a negative temperature control (NTC) thermistor, wherein the controlling further controls the second switch to permit, at a second time after the first time, current to flow from the power source to the load via the second switch, and wherein at an end of the first time, the PTC thermistor has a greater resistance than the NTC thermistor. 16. A system for powering a load comprising: a first switch having a first terminal, a second terminal, and first control terminal; a second switch having a third terminal, a fourth terminal, and a second control terminal; a first thermistor electrically connected to the second terminal of the first switch; and a second thermistor electrically connected to the load, wherein the first thermistor or the second thermistor is a positive temperature control (PTC) thermistor, wherein the other of the first thyristor or the second thermistor is a negative temperature control (NTC) thermistor, wherein the first terminal is configured to be electrically connected to a power source, wherein the first thermistor is electrically connected to the second terminal, wherein the second thermistor is in series with the first thermistor between the second terminal and the load, wherein, during a first time interval, the first switch conducts current and the second switch does not conduct current, wherein, during a second time interval, the first switch does not conduct current and the second switch conducts current, and wherein, at an end of the first time interval, the PCT thermistor has a higher resistance than the NTC thermistor. 17. The system of claim 16 , wherein the first thermistor comprises two or more first thermistors. 18. The system of claim 16 , wherein the second thermistor comprises two or more second thermistors.

Assignees

Inventors

Classifications

  • the cycle being controlled or terminated in response to electric parameters · CPC title

  • with circuits adapted for supplying loads from the battery · CPC title

  • Regulation of charging or discharging current or voltage · CPC title

  • Control of state of charge [SOC] · CPC title

  • including monitoring or indicating arrangements · CPC title

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Frequently asked questions

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What does patent US11509144B2 cover?
A system for suppressing inrush currents is described. The system may include a negative temperature coefficient (NTC) thermistor and a positive temperature coefficient (PTC) thermistor arranged in series between a power source and a battery system to be charged. At a low temperature, while the PTC thermistor provides only minimal resistance to minimize an inrush current, the NTC thermistor pro…
Who is the assignee on this patent?
Inventus Power Inc
What technology area does this patent fall under?
Primary CPC classification H02J7/40. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 22 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).