Method for fabricating memory device

Patent metadata

Field	Value
Publication number	US-11508783-B2
Application number	US-202117235785-A
Country	US
Kind code	B2
Filing date	Apr 20, 2021
Priority date	Apr 15, 2019
Publication date	Nov 22, 2022
Grant date	Nov 22, 2022

Abstract

A method for fabricating memory device is provided. The method includes forming a transistor on a substrate. Further, a contact structure is formed on a source/drain region of the transistor. A conductive layer is formed on the contact structure. Four memory structures are formed on the conductive layer to form a quadrilateral structure.

First claim

What is claimed is:

1. A method for fabricating memory device, comprising:
forming a transistor on a substrate;
forming a contact structure on a source/drain region of the transistor;
forming a conductive layer on the contact structure;
forming four memory structures, comprising forming a bottom electrode of each of the four memory structures on the conductive layer to form a quadrilateral structure, and forming a top electrode over the bottom electrode;
forming a first pair of interconnection lines, respectively connected to the top electrode of each of a first pair of the four memory structures; and
forming a second pair of interconnection lines, respectively connected to the top electrode of each of a second pair of the four memory structures.

2. The method for fabricating memory device as recited in claim 1 , wherein the first pair of the four memory structures extends along a first direction, and the second pair of the four memory structures extends along a second direction, the first direction intersects the second direction.

3. The method for fabricating memory device as recited in claim 1 ,
wherein the first pair of interconnection lines is higher than the second pair of interconnection lines, wherein the first pair of interconnection lines has a protruding portion to contact the first pair of the four memory structures.

4. The method for fabricating memory device as recited in claim 1 , wherein each of the four memory structures is a resistive memory structure or a phase-change memory structure.

5. The method for fabricating a memory device as recited in claim 1 , wherein the conductive layer is single layer.

6. The method for fabricating a memory device as recited in claim 1 , wherein a step of forming the conductive layer comprises:
forming a metal layer on the contact structure; and
forming a via layer on the metal layer, wherein the first pair of the memory structures and the second pair of the memory structures are disposed on the via layer.

7. The method for fabricating memory device as recited in claim 6 , wherein the via layer has a concave at a central region surrounded by a peripheral region, and the four memory structures are disposed on the via layer at the peripheral region.

Assignees

• United Microelectronics Corp
• United Miicroelectronics Corp

Inventors

• Chen Chung-Tse
• Chen Ko-Chi
• Chang Tzu-Yun

Classifications

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• H01L27/2436

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic

• H01L45/16

  Electricity · mapped topic