Microelectronic assemblies

Patent metadata

Field	Value
Publication number	US-11508587-B2
Application number	US-201716648645-A
Country	US
Kind code	B2
Filing date	Dec 29, 2017
Priority date	Dec 29, 2017
Publication date	Nov 22, 2022
Grant date	Nov 22, 2022

Abstract

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; and a die embedded in the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts and the second conductive contacts are electrically coupled to conductive pathways in the package substrate.

First claim

The invention claimed is:

1. A microelectronic assembly, comprising:
a package substrate including a plurality of layers, wherein the plurality of layers include a first layer, a second layer, a third layer, and a fourth layer;
a die having a first surface with first conductive contacts and an opposing second surface with second conductive contacts, wherein the die is embedded in the first layer of the package substrate, and wherein the first and second conductive contacts are coupled to conductive pathways in the package substrate;
a heat spreader in the second layer of the package substrate, wherein the second layer is on the first layer and the heat spreader is in contact with the second surface of the die;
a conductive plane in the third layer of the package substrate, wherein the third layer is on the second layer and the conductive plane is in contact with the heat spreader; and
a channel in the fourth layer of the package substrate, wherein the fourth layer is on the third layer, and wherein the conductive plane provides at least a portion of a wall of the channel.

2. The microelectronic assembly of claim 1 , wherein the die has a thickness between 10 um and 50 um.

3. The microelectronic assembly of claim 1 , wherein the channel is one of a plurality of channels.

4. The microelectronic assembly of claim 1 , further comprising:
a fluid in the channel.

5. The microelectronic assembly of claim 4 , wherein the fluid includes a coolant.

6. The microelectronic assembly of claim 5 , wherein the coolant includes water.

7. The microelectronic assembly of claim 4 , further comprising:
a pump for circulating the fluid through the channel.

8. The microelectronic assembly of claim 1 , wherein the die is a first die, and the microelectronic assembly further comprising:
a second die embedded in a fifth layer of the package substrate, wherein the fifth layer is below the first layer, and wherein the second die at least partially overlaps the first die.

Assignees

• Intel Corp

Inventors

• Elsherbini Adel A
• Liff Shawna M
• Swan Johanna M

Classifications

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title