Display device, display driver, and failure inspection method

Patent metadata

Field	Value
Publication number	US-11508280-B2
Application number	US-202217694487-A
Country	US
Kind code	B2
Filing date	Mar 14, 2022
Priority date	Mar 30, 2021
Publication date	Nov 22, 2022
Grant date	Nov 22, 2022

Abstract

An operational amplifier has a first input terminal and an output terminal connected to a second input terminal of the operational amplifier, and output nodes connected to the source lines of a display panel. During a failure inspection mode, the connection between the output node and the output terminal of the operational amplifier included in another output circuit among one output circuit and the other output circuit is disconnected and the output node instead of the output terminal is connected to the second input terminal of the operational amplifier. A pair of source lines connected to the output nodes of the one output circuit and the other output circuit are linked to each other, and signals attained by acquiring and binarizing voltages outputted from the operational amplifier in the other output circuit as a monitor voltage at different timings are acquired as first and second failure determination signals.

First claim

What is claimed is:

1. A display device, comprising:
a display panel that includes first to nth (n being an integer of 2 or greater) source lines, a linking line, and first to nth source line linking switches that are each connected to respective first ends of the first to nth source lines and that connect the first ends to the linking line when turned ON;
a decoder circuit that generates first to nth drive voltages having a voltage value based on an image signal during a normal mode, and generates n voltages having a test voltage as the first to nth drive voltages during a failure inspection mode;
first to nth output circuits that each include an operational amplifier that is configured to receive a drive voltage via a first input terminal and that has an output terminal connected to a second input terminal, and an output node connected to a second end of each of the source lines, the first to nth output circuits being configured to output, via the output nodes thereof respectively, voltages attained by individually amplifying the first to nth drive voltages in the operational amplifier as first to nth output voltages;
a failure inspection control circuit that, during the failure inspection mode, sets a source line linking switch, among the first to nth source line linking switches, that is connected to one source line and another source line among the first to nth source lines so as to be ON while setting OFF other source line linking switches, disconnects a connection between the output node and the output terminal of the operational amplifier included in another one of the output circuits connected to said another source line among one of the output circuits connected to the one source line and said another one of the output circuits, and connects the output node instead of the output terminal to the second input terminal of the operational amplifier; and
a failure determination circuit that is configured to set a voltage of the output terminal of the operational amplifier included in said another one of the output circuits as a monitor voltage, to store, as a first failure determination signal, a signal attained by acquiring and binarizing the monitor voltage at a first timing, and to store, as a second failure determination signal, a signal attained by acquiring and binarizing the monitor voltage at a second timing delayed from the first timing by a prescribed delay time.

2. The display device according to claim 1 ,
wherein the failure inspection mode includes a reset step of initializing an electric charge amount accumulated in each of the first to nth source lines, and
wherein, during the reset step, the failure inspection control circuit performs control so as to connect the output terminal of the operational amplifier included in each of the first to nth output circuits to each of the output nodes and connect the second input terminal of the operational amplifier to each of the output nodes, and controls all of the first to nth source line linking switches so as to be OFF.

3. The display device according to claim 1 ,
wherein the failure inspection control circuit sequentially changes a combination of a pair of output circuits constituted of said one of the output circuits and said another one of the output circuits among the first to nth output circuits during the failure inspection mode.

4. The display device according to claim 3 ,
wherein the failure determination circuit is provided for each said pair of output circuits.

5. The display device according to claim 1 ,
wherein, during the normal mode, the failure inspection control circuit connects the output terminal of the operational amplifier included in each of the first to nth output circuits to each of the output nodes, controls the second input terminal of the operational amplifier so as to be connected to each of the output nodes, and controls all of the first to nth source line linking switches so as to be OFF.

6. The display device according to claim 1 ,
wherein each of the first to nth output circuits includes:
a first switch that connects the output terminal of the operational amplifier to the output node when turned ON;
a second switch that connects the output terminal of the operational amplifier to the second input terminal of the operational amplifier when turned ON;
a third switch that connects the output terminal of the operational amplifier to a monitor node when turned ON; and
a fourth switch that connects the second input terminal of the operational amplifier to the output node when turned ON.

7. A display device, comprising:
a display panel including first to nth (n being an integer of 2 or greater) source lines;
a decoder circuit that generates first to nth drive voltages having a voltage value based on an image signal during a normal mode, and generates n voltages having a test voltage as the first to nth drive voltages during a failure inspection mode;
first to nth output circuits that each include an operational amplifier that is configured to receive a drive voltage via a first input terminal and that has an output terminal connected to a second input terminal, and an output node connected to each of the source lines, the first to nth output circuits being configured to output, via the output nodes thereof respectively, voltages attained by individually amplifying the first to nth drive voltages in the operational amplifier as first to nth output voltages;
a failure inspection control circuit that, during the failure inspection mode, disconnects a connection between the output node and the output terminal of the operational amplifier included in another one of the output circuits among one of the output circuits connected to one source line among the first to nth source lines and said another one of the output circuits connected to another source line, and connects the output node included in said one of the output circuits, instead of the output terminal, to the second input terminal of the operational amplifier; and
a failure determination circuit that is configured to set a voltage of the output terminal of the operational amplifier included in said another one of the output circuits as a monitor voltage, to store, as a first failure determination signal, a signal attained by acquiring and binarizing the monitor voltage at a first timing, and to store, as a second failure determination signal, a signal attained by acquiring and binarizing the monitor voltage at a second timing delayed from the first timing by a prescribed delay time.

8. The display device according to claim 7 ,
wherein the display device includes:
n external terminals respectively connected to a first end of each of the first to nth source lines; and
first to nth output switches that connect the n external terminals to the output nodes of the first to nth output circuits, respectively, when turned ON.

9. The display device according to claim 7 ,
wherein the failure inspection mode includes a reset step of initializing an electric charge amount accumulated in each of the first to nth source lines, and
wherein, during the reset step, the failure inspection control circuit performs control so as to connect the output terminal of the operational amplifier included in each of the first to nth output circuits to the output node, and so as to connect the second input terminal of the operational amplifier to the output node.

10. The display device according to claim 7 ,
wherein the failure inspection control circuit sequentially changes a combination of said one of the output circuits and said another one of the output circuits from among the first to nth output circuits during the failure inspection mode.

11. The display

Assignees

• Lapis Tech Co Ltd

Inventors

• Ichikura Hiroyoshi

Classifications

• G09G2330/12

  Test circuits or failure detection circuits included in a display system, as permanent part thereof · CPC title

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

• G09G3/36

  using liquid crystals · CPC title

• G09G3/006 Primary

  Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

• G01R31/56

  Testing of electric apparatus (testing of transformers G01R31/62; testing of connections G01R31/66) · CPC title