Maintenance operations in a DRAM

Patent metadata

Field	Value
Publication number	US-11507280-B2
Application number	US-202016875881-A
Country	US
Kind code	B2
Filing date	May 15, 2020
Priority date	Jan 22, 2009
Publication date	Nov 22, 2022
Grant date	Nov 22, 2022

Abstract

A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of a data interface circuit of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

First claim

What is claimed is:

1. A memory controller that controls the operation of a memory device external to the memory controller, the memory device including a command interface, and a plurality of memory banks, each bank including a plurality of rows of memory cells, the memory controller comprising:
a circuit to issue a refresh command to the command interface of the memory device external to the memory controller, wherein the refresh command specifies a refresh operation of the plurality of memory banks, the refresh operation to occur during a time interval; and
the circuit to issue an operation code to the memory device, the operation code specifying a calibration operation to be performed concurrently with the refresh operation during the time interval, of the command interface of the memory device, wherein the circuit to issue the refresh command is to issue a calibration pattern to the command interface of the memory device during the calibration operation, the calibration pattern comprising a data pattern for calibrating the command interface of the memory device.

2. The memory controller of claim 1 , wherein the operation code is sent to the memory device with the refresh command such that the operation code is issued as part of the refresh command.

3. The memory controller of claim 1 , wherein the refresh command includes a plurality of bits to identify at least one bank as a first bank of the plurality of memory banks to be refreshed in a sequence in response to the refresh command.

4. The memory controller of claim 3 , wherein the refresh operation is specified as an auto-refresh operation, wherein a row of memory cells is refreshed in the at least one bank identified by the plurality of bits.

5. The memory controller of claim 1 , wherein the circuit to issue the refresh command is a circuit to transmit the refresh command, along with a plurality of bits, to the command interface of the memory device, the plurality of bits to identify at least one bank as a first bank of the plurality of memory banks to be refreshed in a sequence during the time interval.

6. The memory controller of claim 1 , further including a circuit to generate the calibration pattern; wherein the circuit to issue the refresh command and issue the calibration pattern to the command interface of the memory device during the calibration operation issues the calibration pattern to the command interface of the memory device via a data path from the memory controller to the memory device external to the memory controller.

7. The memory controller of claim 1 , wherein a data interface circuit of the memory device includes an on-die termination circuit having a termination resistance, and the circuit to issue an operation code to the memory device is configured to issue a respective operation code specifying a calibration operation of the termination resistance of the on-die termination circuit.

8. The memory controller of claim 7 , wherein the data interface circuit of the memory device includes an output driver having an output drive strength, and the circuit to issue an operation code to the memory device is configured to issue a second operation code specifying a calibration operation of the output drive strength.

9. The memory controller of claim 1 , wherein the operation code specifying the calibration operation is to cause the command interface of the memory device to operate in a loopback mode, in which the command interface of the memory device receives the calibration pattern on a first data path and transmits the calibration pattern to the memory controller on a second data path, for at least a portion of the time interval during which the refresh operation occurs.

10. A method of operating a memory controller that controls the operation of a memory device external to the memory controller, the memory device including a command interface, and a plurality of memory banks, each bank including a plurality of rows of memory cells, the method comprising:
the memory controller issuing a refresh command to the command interface of the memory device external to the memory controller, wherein the refresh command specifies a refresh operation of the plurality of memory banks of the memory device, the refresh operation to occur during a time interval; and
the memory controller issuing an operation code to the memory device, the operation code specifying a calibration operation to be performed concurrently with the refresh operation during the time interval, of the command interface of the memory device, and issuing a calibration pattern to the command interface of the memory device during the calibration operation, the calibration pattern comprising a data pattern for calibrating the command interface of the memory device.

11. The method of claim 10 , wherein the operation code is sent to the memory device with the refresh command such that the operation code is issued as part of the refresh command.

12. The method of claim 10 , wherein the refresh command includes a plurality of bits to identify at least one bank as a first bank of the plurality of memory banks to be refreshed in a sequence in response to the refresh command.

13. The method of claim 12 , wherein the refresh operation is specified as an auto-refresh operation, wherein a row of memory cells is refreshed in the at least one bank identified by the plurality of bits.

14. The method of claim 10 , wherein issuing the refresh command comprises issuing the refresh command along with a plurality of bits to the command interface of the memory device, the plurality of bits to identify at least one bank as a first bank of the plurality of memory banks to be refreshed in a sequence during the time interval.

15. The method of claim 10 , including the memory controller generating the calibration pattern, and issuing the calibration pattern to the command interface of the memory device via a data path from the memory controller to the memory device external to the memory controller.

16. The method of claim 10 , wherein a data interface circuit of the memory device includes an on-die termination circuit having a termination resistance, and a respective calibration operation specified by a respective operation code issued by the memory controller is a calibration operation of the termination resistance of the on-die termination circuit.

17. The method of claim 16 , wherein the data interface circuit of the memory device includes an output driver having an output drive strength, and the method includes issuing a second operation code to the memory device, the second operation code specifying a calibration operation of the output drive strength.

18. The method of claim 10 , including, at a data interface of the memory controller, receiving data from a data interface of the memory device during a data transfer mode and receiving a respective calibration pattern from the data interface of the memory device during a respective calibration operation to calibrate the data interface of the memory device.

19. A memory controller that controls the operation of a memory device external to the memory controller, the memory device including a command interface, and a plurality of memory banks, each bank including a plurality of rows of memory cells, the memory controller comprising:
means for issuing a refresh command to the command interface of the memory device external to the memory controller, wherein the refresh command specifies a refresh operation of the plurality of memory banks of the memory device, the refresh operation to occur during a

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Palmer Robert E
• Poulton John W

Classifications

• G11C7/02

  with means for avoiding parasitic signals · CPC title

• G11C11/40618

  Refresh operations over multiple banks or interleaving · CPC title

• G11C2211/4061

  Calibration or ate or cycle tuning · CPC title

• G06Q10/00

  Administration; Management · CPC title

• G11C11/40615

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title