Semiconductor structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11502195-B2
Application number	US-202017010846-A
Country	US
Kind code	B2
Filing date	Sep 3, 2020
Priority date	Dec 26, 2019
Publication date	Nov 15, 2022
Grant date	Nov 15, 2022

Abstract

A semiconductor structure and a manufacturing method of the semiconductor structure are provided. The semiconductor structure includes a substrate and a III-V group compound layer disposed on the substrate. The III-V group compound layer has n trenches vertically communicating with each other, and n≥2. Widths of the n trenches gradually decrease from the width of the uppermost first trench to the width of the lowermost n th trench, and the n th trench exposes a portion of the substrate.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate; and
a III-V group compound layer, disposed on the substrate,
wherein the III-V group compound layer has n trenches vertically communicating with each other, and n≥2, wherein widths of the n trenches gradually decrease from the width of the uppermost first trench to the width of the lowermost n th trench;
wherein the n th trench exposes a portion of the substrate, and
wherein the n trenches have a total depth D, and a depth of each of the n trenches is within a range of D/n±50%.

2. The semiconductor structure according to claim 1 , wherein the n th trench exposes a surface of the substrate.

3. The semiconductor structure according to claim 1 , wherein the n th trench exposes a portion of the substrate and extends into the substrate.

4. The semiconductor structure according to claim 1 , wherein an angle between a sidewall of each of the n trenches and a surface of the substrate ranges from 30° to 90°.

5. The semiconductor structure according to claim 1 , wherein the III-V group compound layer comprises a gallium nitride layer.

6. The semiconductor structure according to claim 1 , wherein the n trenches form a staircase structure.

7. The semiconductor structure according to claim 1 , wherein sidewalls of the n trenches are all perpendicular to a plane where the substrate is located.

8. The semiconductor structure according to claim 1 , wherein sidewalls of the n trenches are inclined sidewalls.

9. The semiconductor structure according to claim 1 , wherein the substrate comprises a silicon substrate.

10. The semiconductor structure according to claim 1 , wherein the n trenches penetrate the III-V group compound layer.

11. A manufacturing method of a semiconductor structure, comprising:
providing a substrate;
forming a III-V group compound layer on the substrate; and
sequentially forming n trenches vertically communicating with each other in the III-V group compound layer,
wherein widths of the n trenches gradually decrease from the width of the uppermost first trench to the width of the lowermost n th trench, the n th trench exposes a portion of the substrate, and n≥2, and
wherein the n trenches have a total depth D, and a depth of each of the n trenches is within a range of D/n±50%.

12. The manufacturing method according to claim 11 , wherein the n th trench exposes a surface of the substrate.

13. The manufacturing method according to claim 11 , wherein the n th trench extends into the substrate.

14. The manufacturing method according to claim 11 , wherein an angle between a sidewall of each of the n trenches and a surface of the substrate ranges from 30° to 90°.

15. The manufacturing method according to claim 11 , wherein the III-V group compound layer comprises a gallium nitride layer.

16. The manufacturing method according to claim 11 , wherein the n trenches are formed in an order from the first trench to the n th trench.

17. The manufacturing method according to claim 11 , wherein the n trenches form a staircase structure.

18. The manufacturing method according to claim 11 , wherein sidewalls of the n trenches are all perpendicular to a plane where the substrate is located.

19. A semiconductor structure, comprising:
a substrate; and
a group compound layer, disposed on the substrate, wherein the III-V group compound layer has n trenches vertically communicating with each other, and n≥2, wherein widths of the n trenches gradually decrease from the width of the uppermost first trench to the width of the lowermost n th trench, the n trenches have a total depth D, and a depth of each of the n trenches is within a range of D/n±50%.

Assignees

• Nuvoton Technology Corp

Inventors

• Wang Ching-San
• Chen Kuang-Chu
• Hsiao Peng-Chan
• Liu han-ying

Classifications

• H10P14/3416

  Nitrides · CPC title

• H01L29/2003

  Electricity · mapped topic

• H01L29/7842 Primary

  Electricity · mapped topic

• H01L29/4236

  Electricity · mapped topic

• H01L29/66734

  Electricity · mapped topic