Semiconductor device and method of producing a semiconductor device

Patent metadata

Field	Value
Publication number	US-11501979-B1
Application number	US-202117350345-A
Country	US
Kind code	B1
Filing date	Jun 17, 2021
Priority date	Jun 17, 2021
Publication date	Nov 15, 2022
Grant date	Nov 15, 2022

Abstract

A semiconductor device and a method of producing the semiconductor device are described. The semiconductor device includes: a semiconductor substrate; a metallization layer over the semiconductor substrate; a plating over the metallization layer, the plating including NiP; a passivation over the metallization layer and laterally adjacent the plating such that a surface of the plating that faces away from the semiconductor substrate is uncovered by the passivation, wherein a seam is present along an interface between the passivation and the plating; and a structure that covers the seam along a periphery of the plating and delimits a bondable area for the plating. The structure extends from the periphery of the plating onto the passivation. The structure includes an imide having a curing temperature below a recrystallization temperature of the NiP or an oxide having a deposition temperature below the recrystallization temperature of the NiP.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate;
a metallization layer over the semiconductor substrate;
a plating over the metallization layer, the plating comprising NiP;
a passivation over the metallization layer and laterally adjacent the plating such that a surface of the plating that faces away from the semiconductor substrate is uncovered by the passivation, wherein a seam is present along an interface between the passivation and the plating; and
a structure that covers the seam along a periphery of the plating and delimits a bondable area for the plating,
wherein the structure extends from the periphery of the plating onto the passivation,
wherein the structure comprises an imide having a curing temperature below a recrystallization temperature of the NiP or an oxide having a deposition temperature below the recrystallization temperature of the NiP.

2. The semiconductor device of claim 1 , wherein the passivation comprises a stack of electrically insulative layers, wherein an uppermost layer of the stack of electrically insulative layers is an oxide or silicon nitride layer, and wherein the structure extends from the periphery of the plating onto the oxide or silicon nitride layer.

3. The semiconductor device of claim 1 , wherein the passivation comprises a stack of electrically insulative layers, wherein an uppermost layer of the stack of electrically insulative layers is a polyimide layer, wherein the polyimide layer is pulled back to form a step, and wherein the structure extends from the periphery of the plating onto the step.

4. The semiconductor device of claim 3 , wherein the electrically insulative layer of the stack of electrically insulative layers immediately below the polyimide layer is an oxide or silicon nitride layer, wherein the structure comprises the imide having the curing temperature below the recrystallization temperature of the NiP, and wherein the structure contacts a section of the oxide or silicon nitride layer uncovered by the polyimide layer and which forms the step.

5. The semiconductor device of claim 3 , wherein the electrically insulative layer of the stack of electrically insulative layers immediately below the polyimide layer is an oxide or silicon nitride layer, wherein the structure comprises the oxide having the deposition temperature below the recrystallization temperature of the NiP, and wherein the structure is interposed between the oxide or silicon nitride layer and the polyimide layer.

6. The semiconductor device of claim 3 , wherein the structure is thinner than the polyimide layer, and wherein the structure contacts a sidewall of the polyimide layer that delimits the step.

7. The semiconductor device of claim 3 , wherein the structure is thicker than the polyimide layer, and wherein the structure extends from the periphery of the plating onto a surface of the polyimide layer that faces away from the semiconductor substrate.

8. The semiconductor device of claim 1 , wherein an uppermost layer of the passivation is a polyimide layer, wherein the polyimide layer is pulled back such that a gap is present between a sidewall of the plating and a sidewall of the polyimide layer, wherein the gap is wider than the seam, and wherein the structure fills the gap between the sidewall of the plating and the sidewall of the polyimide layer.

9. The semiconductor device of claim 1 , wherein an uppermost layer of the passivation is an oxide or silicon nitride layer, wherein the structure comprises the imide having the curing temperature below the recrystallization temperature of the NiP, and wherein the structure covers the entire passivation.

10. The semiconductor device of claim 1 , wherein the plating further comprises a noble metal over the NiP.

11. The semiconductor device of claim 1 , wherein the metallization layer comprises an aluminum compound.

12. A method of producing a semiconductor device, the method comprising:
forming a metallization layer over a semiconductor substrate;
forming a passivation over the metallization layer;
forming a plating that comprises NiP over the metallization layer, wherein the passivation is laterally adjacent the plating such that a surface of the plating that faces away from the semiconductor substrate is uncovered by the passivation, wherein a seam is present along an interface between the passivation and the plating; and
forming a structure that covers the seam along a periphery of the plating and delimits a bondable area for the plating,
wherein the structure extends from the periphery of the plating onto the passivation,
wherein forming the structure comprises curing an imide at a curing temperature below a recrystallization temperature of the NiP or depositing an oxide at a deposition temperature below the recrystallization temperature of the NiP.

13. The method of claim 12 , wherein:
forming the passivation comprises forming a stack of electrically insulative layers over the metallization layer, an uppermost layer of the stack of electrically insulative layers being an oxide or silicon nitride layer; and
the structure is formed so as to extend from the periphery of the plating onto the oxide or silicon nitride layer.

14. The method of claim 12 , wherein:
forming the passivation comprises forming a stack of electrically insulative layers over the metallization layer, an uppermost layer of the stack of electrically insulative layers being a polyimide layer, the polyimide layer being pulled back to form a step; and
the structure is formed so as to extend from the periphery of the plating onto the step.

15. The method of claim 14 , wherein:
the electrically insulative layer of the stack of electrically insulative layers immediately below the polyimide layer is an oxide or silicon nitride layer;
forming the structure comprises curing the imide at the curing temperature below the recrystallization temperature of the NiP; and
the structure contacts a section of the oxide or silicon nitride layer uncovered by the polyimide layer and which forms the step.

16. The method of claim 14 , wherein:
the electrically insulative layer of the stack of electrically insulative layers immediately below the polyimide layer is an oxide or silicon nitride layer; and
forming the structure comprises depositing, over the oxide or silicon nitride layer before the polyimide layer is formed, the oxide at the deposition temperature below the recrystallization temperature of the NiP such that the structure is interposed between the oxide or silicon nitride layer and the polyimide layer.

17. The method of claim 14 , wherein the structure is thinner than the polyimide layer, and wherein the structure is formed so as to contact a sidewall of the polyimide layer that delimits the step.

18. The method of claim 14 , wherein the structure is thicker than the polyimide layer, and wherein the structure is formed so as to extend from the periphery of the plating onto a surface of the polyimide layer that faces away from the semiconductor substrate.

19. The method of claim 12 , wherein:
forming the passivation comprises forming a polyimide layer over an oxide or silicon nitride layer, the polyimide layer being an uppermost layer of the passivation, the polyimide layer being pulled back such that a gap is present between a sidewall of the plating and a sidewall of the polyimide layer, the gap being wider than the seam; and
the structure is formed so as to fill the gap between the sidewall of the plating and the sidewall of the polyimide layer.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Beninger-Bina Markus
• Behrendt Andreas
• Harrison Mark
• Hartl Robert
• Imrich Peter
• Lindner Reinhard
• Napetschnig Evelyn

Classifications

• H10P90/1914

  using bonding · CPC title

• H10D64/01354

  passivation or protection of the electrode, e.g. using re-oxidation · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title