Volatile memory device and data sensing method thereof

Patent metadata

Field	Value
Publication number	US-11501824-B2
Application number	US-202017002002-A
Country	US
Kind code	B2
Filing date	Aug 25, 2020
Priority date	Feb 5, 2020
Publication date	Nov 15, 2022
Grant date	Nov 15, 2022

Abstract

A volatile memory device includes: a first sense amplifier connected to a first memory cell through a first bit line, and configured to sense 2-bit data stored in the first memory cell; a second sense amplifier connected to a second memory cell through a second bit line, and configured to sense 2-bit data stored in the second memory cell, the second bit line having a length greater than a length of the first bit line; and a driving voltage supply circuit configured to supply a first driving voltage to the first sense amplifier, and supply a second driving voltage to the second sense amplifier, the second driving voltage having a voltage level different from a voltage level of the first driving voltage.

First claim

What is claimed is:

1. A volatile memory device comprising:
a first sense amplifier connected to a first memory cell through a first bit line, and configured to sense 2-bit data stored in the first memory cell;
a second sense amplifier connected to a second memory cell through a second bit line, and configured to sense 2-bit data stored in the second memory cell, the second bit line having a length greater than a length of the first bit line; and
a driving voltage supply circuit configured to supply a first driving voltage to the first sense amplifier, and supply a second driving voltage to the second sense amplifier, the second driving voltage having a voltage level different from a voltage level of the first driving voltage,
wherein the first sense amplifier is not connected to the second bit line, and the second sense amplifier is not connected to the first bit line.

2. The volatile memory device of claim 1 , wherein the driving voltage supply circuit is further configured to:
precharge the first bit line using a first precharge voltage by supplying the first precharge voltage in a precharge period of a sensing operation on the first memory cell; and
precharge the second bit line using a second precharge voltage by supplying the second precharge voltage in a precharge period of a sensing operation on the second memory cell,
wherein the second precharge voltage is different from the first precharge voltage.

3. The volatile memory device of claim 2 , wherein a difference between the first precharge voltage and the second precharge voltage corresponds to a difference between a capacitance of the first bit line and a capacitance of the second bit line.

4. The volatile memory device of claim 1 , wherein the first sense amplifier comprises:
a first latch configured to sense a least significant bit (LSB) of the 2-bit data stored in the first memory cell, and latch the LSB to a first sensing bit line pair; and
a second latch configured to sense a most significant bit (MSB) of the 2-bit data stored in the first memory cell, and latch the MSB to a second sensing bit line pair, and wherein the second sense amplifier comprises:
a third latch configured to sense an LSB of the 2-bit data stored in the second memory cell, and latch the LSB to a third sensing bit line pair; and
a fourth latch configured to sense an MSB of the 2-bit data stored in the second memory cell, and latch the MSB to a fourth sensing bit line pair.

5. The volatile memory device of claim 4 , wherein the driving voltage supply circuit is further configured to:
supply a first power supply voltage having a first voltage level to the first sense amplifier to drive a pull-up terminal of the first latch in at least one of an MSB sensing operation period and an LSB sensing operation period of a sensing operation on the first memory cell; and
supply the first power supply voltage having a second voltage level to the second sense amplifier to drive a pull-up terminal of the third latch in at least one of an MSB sensing operation period and an LSB sensing operation period of a sensing operation on the second memory cell.

6. The volatile memory device of claim 5 , wherein a difference between the first voltage level and the second voltage level corresponds to a difference between the length of the first bit line and the length of the second bit line.

7. The volatile memory device of claim 4 , wherein the driving voltage supply circuit is further configured to:
supply a first power supply voltage having a first voltage level to the first sense amplifier to drive a pull-up terminal of the second latch in an MSB sensing operation period of a sensing operation on the first memory cell; and
supply the first power supply voltage having a second voltage level to the second sense amplifier to drive a pull-up terminal of the fourth latch in an MSB sensing operation period of a sensing operation on the second memory cell.

8. The volatile memory device of claim 7 , wherein a difference between the first voltage level and the second voltage level corresponds to a voltage level for compensating for a difference between a sensing characteristic of the first sense amplifier and a sensing characteristic of the second sense amplifier.

9. The volatile memory device of claim 4 , wherein the driving voltage supply circuit is further configured to:
supply a first power supply voltage having a first voltage level to the first sense amplifier to drive a pull-up terminal of the second latch in a restore operation period of a sensing operation on the first memory cell; and
supply the first power supply voltage having a second voltage level to the second sense amplifier to drive a pull-up terminal of the fourth latch in a restore operation period of a sensing operation on the second memory cell.

10. The volatile memory device of claim 9 , wherein the driving voltage supply circuit is further configured to:
supply a first pull-down voltage having a third voltage level to the first sense amplifier to drive a pull-down terminal of the second latch in the restore operation period of the sensing operation on the first memory cell; and
supply the first pull-down voltage having a fourth voltage level to the second sense amplifier to drive a pull-down terminal of the fourth latch in the restore operation period of the sensing operation on the second memory cell.

11. A data sensing method of a volatile memory device, the data sensing method comprising:
precharging a first bit line using a first precharge voltage;
sensing first 2-bit data through a first sense amplifier connected to the first bit line, the first 2-bit data being stored in a first memory cell connected between the first bit line and a selected word line;
precharging a second bit line using a second precharge voltage different from the first precharge voltage, the second bit line having a length greater than a length of the first bit line; and
sensing second 2-bit data through a second sense amplifier connected to the second bit line, the second 2-bit data being stored in a second memory cell connected between the second bit line and the selected word line,
wherein the first sense amplifier is not connected to the second bit line, and the second sense amplifier is not connected to the first bit line.

12. The data sensing method of claim 11 , wherein a difference between the first precharge voltage and the second precharge voltage corresponds to a level for compensating for a difference between a sensing characteristic of the first sense amplifier and a sensing characteristic of the second sense amplifier.

13. The data sensing method of claim 11 , wherein the sensing the first 2-bit data comprises:
sensing a most significant bit (MSB) of the first 2-bit data using a first latch driven based on a first power supply voltage; and
latching the MSB of the first 2-bit data in a second latch driven based on a second power supply voltage, and
wherein the sensing the second 2-bit data comprises:
sensing an MSB of the second 2-bit data using a third latch driven based on a third power supply voltage; and
latching the MSB of the second 2-bit data in a fourth latch driven based on a fourth power supply voltage.

14. The data sensing method of claim 13 , wherein a voltage level of the first power supply voltage is different from a voltage level of the third power supply voltage, and
wherein a difference between the voltage level of the first power supply voltage and the voltage level of the third power supply voltage corresponds to a difference between a capacitance of the first bit line and a capacitance of the second bit line.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Dongil
• Seo Younghun

Classifications

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title