ZNS parity swapping to DRAM

Patent metadata

Field	Value
Publication number	US-11500727-B2
Application number	US-202016884569-A
Country	US
Kind code	B2
Filing date	May 27, 2020
Priority date	May 27, 2020
Publication date	Nov 15, 2022
Grant date	Nov 15, 2022

Abstract

The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. A first command to write data to a first zone is received, first XOR data is generated in the RAM1, and the data of the first command is written to the first zone. When a second command to write data to a second zone is received, the generated first XOR data is copied from the RAM1 to the RAM2, and second XOR data for the second zone is copied from the RAM2 to the RAM1. The second XOR data is updated with the second command, and the data of the second command is written to the second zone. The updated second XOR data is copied from the RAM1 to the RAM2.

First claim

What is claimed is:

1. A storage device, comprising:
a non-volatile storage unit, wherein a capacity of the non-volatile storage unit is divided into a plurality of zones, and wherein the non-volatile storage unit comprises a plurality of dies, each of the plurality of dies comprising a plurality of erase blocks;
a first volatile memory unit; and
a controller coupled to the non-volatile storage unit and the first volatile memory unit, the controller comprising a second volatile memory unit, wherein the controller is configured to:
receive commands to write data to one or more zones of the plurality of zones;
generate first parity data for a first zone in the second volatile memory unit;
upon receiving a first new command to write first data to a second zone, copy second parity data for the second zone from the first volatile memory unit to the second volatile memory unit;
update the second parity data for the second zone stream to updated second parity data in the second volatile memory unit;
upon receiving a second new command to write second data to the first zone, update the first parity data for the first zone to updated first parity data in the second volatile memory unit; and
in response to updating the first parity data, copy the updated first parity data from the second volatile memory unit to the first volatile memory unit.

2. The storage device of claim 1 , wherein the controller is further configured to erase the first parity data and the second parity data from the second volatile memory.

3. The storage device of claim 1 , wherein the updated first parity data for the first zone is copied from the second volatile memory unit to the first volatile memory unit when a controller buffer area of the second volatile memory unit is filled to capacity, the controller buffer area temporarily storing data to be written to the non-volatile storage unit.

4. The storage device of claim 1 , wherein the controller is further configured to write the first data to the first zone while simultaneously generating the first parity data for the first zone.

5. The storage device of claim 1 , wherein the controller is further configured to:
write the second data to the second zone while simultaneously updating the second parity data for the second zone; and
in response to updating the second parity data, copy the updated second parity data from the second volatile memory unit to the first volatile memory unit.

6. The storage device of claim 1 , wherein the non-volatile storage unit is a NAND memory unit, and wherein the controller comprises an XOR engine.

7. The storage device of claim 6 , wherein the XOR engine is configured to:
generate the first parity data for the first zone in the second volatile memory unit;
update the second parity data for the second zone in the second volatile memory unit; and
update the first parity data for the first zone in the second volatile memory unit.

8. A storage device, comprising:
a non-volatile storage unit, wherein a capacity of the non-volatile storage unit is divided into a plurality of zones, and wherein the non-volatile storage unit comprises a plurality of dies, each of the plurality of dies comprising a plurality of erase blocks;
a first volatile memory unit; and
a controller coupled to the non-volatile storage unit and the first volatile memory unit, the controller comprising a second volatile memory unit, wherein the controller is configured to:
receive a first command to write first data to a first zone of the plurality of zones in the non-volatile storage unit;
generate first parity data for the first data and write the first data to the first zone simultaneously, wherein the first parity data is stored in the second volatile memory unit;
receive a second command to write second data to a second zone in the non-volatile storage unit;
upon receiving the second command, copy second parity data associated with the second zone from the first volatile memory unit to the second volatile memory unit; and
update the second parity data with the second data and write the second data to the second zone simultaneously; and
in response to updating the second parity data, copy the updated second parity data from the second volatile memory unit to the first volatile memory unit.

9. The storage device of claim 8 , wherein the controller is further configured to copy the first parity data from the second volatile memory unit to the first volatile memory unit once a controller buffer area of the second volatile memory unit is filled to capacity, the controller buffer area temporarily storing data to be written to the non-volatile storage unit.

10. The storage device of claim 8 , wherein the controller further comprises an XOR engine, and wherein the XOR engine is configured to generate the first parity data and update the second parity data.

11. The storage device of claim 8 , wherein the first volatile memory unit is a DRAM unit.

12. The storage device of claim 8 , wherein the second volatile memory unit is a SRAM unit.

13. The storage device of claim 8 , wherein the non-volatile storage unit is a NAND memory unit.

14. The storage device of claim 8 , wherein the controller is further configured to:
receive a third command to write third data to the first zone in the non-volatile storage unit;
update the first parity data with the third data in the second volatile memory unit and write the third data to the first zone simultaneously; and
upon updating the first parity data, copy the updated first parity data from the second volatile memory unit to the first volatile memory unit.

15. A storage device, comprising:
a non-volatile storage unit, wherein a capacity of the non-volatile storage unit is divided into a plurality of zones, and wherein the non-volatile storage unit comprises a plurality of dies, each of the plurality of dies comprising a plurality of erase blocks;
a DRAM unit; and
a controller coupled to the non-volatile storage unit and the DRAM unit, the controller comprising a SRAM unit, wherein the controller is configured to:
receive a first command to write data to a first zone of the plurality of zones in the non-volatile storage unit;
update first parity data with the data associated with first command in a first location of the SRAM unit, and simultaneously, write the data associated with the first command to the first zone;
receive a second command to write data to a second zone in the non-volatile storage unit;
copy the updated first parity data from the SRAM unit to the DRAM unit, and simultaneously, copy second parity data associated with the second zone from the DRAM unit to a second location in the SRAM unit;
update the second parity data with the data associated with second command and write the data associated with the second command to the second zone simultaneously;
receive a third command to write data to a third zone in the non-volatile storage unit;
erase the updated first parity data from the first location in the SRAM unit; and
generate third parity data in the first location of the SRAM unit, and simultaneously, write the data associated with the third command to the first zone.

16. The storage device of claim 15 , wherein the controller is further configured to copy the updated second parity data from the SRAM unit to the DRAM unit as the updated first parity data is erased and as the third parity data is generated.

17. The storage device of claim 15 , wherein the controller comprises a parity engine, the parity engine being configured to generate and update parity data for th

Assignees

• Western Digital Tech Inc

Inventors

• Helmick Daniel L
• Parker Liam
• Bennett Alan D
• Grayson Peter
• Gorobets Sergey Anatolievich

Classifications

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F2212/7204

  Capacity control, e.g. partitioning, end-of-life degradation · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title