Sincos encoder interface

Patent metadata

Field	Value
Publication number	US-11499847-B2
Application number	US-202117355248-A
Country	US
Kind code	B2
Filing date	Jun 23, 2021
Priority date	Dec 6, 2018
Publication date	Nov 15, 2022
Grant date	Nov 15, 2022

Abstract

In an example, a circuit includes a first comparator, a second comparator, a pulse counter, a processor, a first ADC, and a second ADC. The first comparator has a first input coupled to a first node, a second input, and an output. The second comparator has a first input coupled to a second node, a second input, and an output. A first DAC is coupled to the second input of the first comparator. A second DAC is coupled to the second input of the second comparator. The pulse counter has a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. The first ADC has an input coupled to the first node and an output coupled to the processor. The second ADC has an input coupled to the second node and an output coupled to the processor.

First claim

What is claimed is:

1. A circuit, comprising:
a first comparator having a first input coupled to a first node, a second input, and an output;
a second comparator having a first input coupled to a second node, a second input, and an output;
a first digital-to-analog converter (DAC) having an output coupled to the second input of the first comparator;
a second DAC having an output coupled to the second input of the second comparator;
a pulse counter having a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and an output;
a processor having a first input and a second input;
a first analog-to-digital converter (ADC) having an input coupled to the first node and an output coupled to the first input of the processor; and
a second ADC having an input coupled to the second node and an output coupled to the second input of the processor.

2. The circuit of claim 1 , wherein a first sine wave is received at the first node and converted by the first comparator to a first square wave, wherein a first cosine wave is received at the second node and converted by the second comparator to a second square wave, wherein the first ADC converts the first sine wave to a first digital value, and wherein the second ADC converts the first cosine wave to a second digital value.

3. The circuit of claim 2 , wherein the pulse counter counts a number of rising edges of the first square wave and the second square wave to determine coarse position information, and wherein the processor is configured to generate fine position information based at least partially on the first digital value and the second digital value.

4. The circuit of claim 1 , further comprising:
a third comparator having a first input coupled to a third node, a second input, and an output coupled to a third input of the pulse counter; and
a third DAC having an output coupled to the second input of the third comparator.

5. The circuit of claim 4 , wherein the first DAC, the second DAC, and the third DAC are configured to receive separate digital values configured to compensate for direct current (DC) bias in signals present at the first node, the second node, and the third node, respectively.

6. The circuit of claim 4 , wherein an index signal is received at the third node and the third comparator is configured to convert the index signal to a third square wave, and wherein the pulse counter is configured to reset a count each time a rising edge of the third square wave is received.

7. The circuit of claim 1 , wherein the processor has a third input and a fourth input and further comprising:
a third ADC having an input coupled to a fourth node and an output coupled to the third input of the processor; and
a fourth ADC having an input coupled to a fifth node and an output coupled to the fourth input of the processor.

8. The circuit of claim 7 , wherein a second sine wave is received at the fourth node and converted to a third digital value by the third ADC, and wherein a second cosine wave is received at the fifth node and converter to a fourth digital value by the fourth ADC.

9. The circuit of claim 8 , wherein the processor is configured to generate absolute position information based at least partially on the third digital value and the fourth digital value.

10. A circuit, consisting essentially of:
a first comparator having a first input coupled to a first node, a second input, and an output;
a second comparator having a first input coupled to a second node, a second input, and an output;
a first digital-to-analog converter (DAC) having an output coupled to the second input of the first comparator;
a second DAC having an output coupled to the second input of the second comparator;
a pulse counter having a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and an output;
a processor having a first input, a second input, a third input, and a fourth input;
a first analog-to-digital converter (ADC) having an input coupled to the first node and an output coupled to the first input of the processor;
a second ADC having an input coupled to the second node and an output coupled to the second input of the processor;
a third comparator having a first input coupled to a third node, a second input, and an output coupled to a third input of the pulse counter;
a third DAC having an output coupled to the second input of the third comparator;
a third ADC having an input coupled to a fourth node and an output coupled to the third input of the processor; and
a fourth ADC having an input coupled to a fifth node and an output coupled to the fourth input of the processor.

11. The circuit of claim 10 , wherein a first sine wave is received at the first node and converted by the first comparator to a first square wave, wherein a first cosine wave is received at the second node and converted by the second comparator to a second square wave, wherein the first ADC converts the first sine wave to a first digital value, wherein the second ADC converts the first cosine wave to a second digital value, wherein an index signal is received at the third node and the third comparator is configured to convert the index signal to a third square wave, wherein a second sine wave is received at the fourth node and converted to a third digital value by the third ADC, and wherein a second cosine wave is received at the fifth node and converted to a fourth digital value by the fourth ADC.

12. The circuit of claim 11 , wherein the pulse counter is configured to:
count a number of rising edges of the first square wave and the second square wave to determine coarse position information; and
reset the count of the number of rising edges of the first square wave and the second square wave each time a rising edge of the third square wave is received, and
wherein the processor is configured to:
generate fine position information based at least partially on the first digital value and the second digital value; and
generate absolute position information based at least partially on the third digital value and the fourth digital value.

13. The circuit of claim 12 , wherein the pulse counter is further configured to count a number of the rising edges of the third square wave to determine a number of revolutions.

14. The circuit of claim 11 , wherein the first comparator and the first ADC receive the first sine wave substantially simultaneously, and wherein the second comparator and the second ADC receive the first cosine wave substantially simultaneously.

15. The circuit of claim 11 , wherein the circuit is implemented on a single die enclosed within a single electrical chip package.

16. An electrical chip consisting essentially of:
a single circuit board; and
a single electrical chip package surrounding the single circuit board,
wherein the single circuit board consists essentially of:
a first comparator having a first input coupled to a first node, a second input, and an output;
a second comparator having a first input coupled to a second node, a second input, and an output;
a first digital-to-analog converter (DAC) having an output coupled to the second input of the first comparator;
a second DAC having an output coupled to the second input of the second comparator;
a pulse counter having a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and an output;
a processor having a first input, a second input, a third input, and a fourth input;
a first an

Assignees

• Texas Instruments Inc

Inventors

• Poley Richard Mark
• Chakravarthy Srinivasa

Classifications

• G01D5/34753

  Carriages; Driving or coupling means · CPC title

• G01D5/2451 Primary

  Incremental encoders (G01D5/2454 takes precedence) · CPC title

• G01D5/245 Primary

  using a variable number of pulses in a train · CPC title

• H02K11/215

  Magnetic effect devices, e.g. Hall-effect or magneto-resistive elements · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title