Predistortion method and system for a non-linear device-under-test

US11496166B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-11496166-B1
Application numberUS-202117464191-A
CountryUS
Kind codeB1
Filing dateSep 1, 2021
Priority dateSep 1, 2021
Publication dateNov 8, 2022
Grant dateNov 8, 2022

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Abstract

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The present disclosure relates to a predistortion method and a predistortion system for a non-linear device-under-test, DUT. The predistortion method comprises the steps of: providing a reference input waveform to the DUT; deriving a predistorted waveform for the DUT based on the reference input waveform using an iterative direct digital predistortion technique; analyzing a relationship between the reference input waveform and the calculated predistorted waveform using a mathematical model; deriving a predistortion algorithm for the DUT based on said analysis; and applying said predistortion algorithm to an input signal and feeding the, thus, predistorted input signal to the DUT.

First claim

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The invention claimed is: 1. A predistortion method for a non-linear device-under-test, DUT, comprising: providing a reference input waveform to the DUT; deriving a predistorted waveform for the DUT based on the reference input waveform using an iterative direct digital predistortion technique; analyzing a relationship between the reference input waveform and the derived predistorted waveform using a mathematical model, wherein the mathematical model comprises a Hammerstein model, a Wiener model, or a Volterra series model; deriving a predistortion algorithm for the DUT based on said analysis; and applying said predistortion algorithm to an input signal and feeding the, thus, predistorted input signal to the DUT. 2. The method of claim 1 , wherein the predistortion algorithm compensates non-linear distortions as well as memory effects of the DUT. 3. The method of claim 1 , wherein the mathematical model comprises a memory polynomial model. 4. The method of claim 3 , wherein a starting point for the Hammerstein model is chosen randomly, and, in case the randomly chosen starting point does not converge, a different starting point is used. 5. The method of claim 1 , wherein the step of analyzing the relationship between the reference input waveform and the derived predistorted waveform using the mathematical model comprises calculating parameters of the mathematical model, wherein said parameters depend on a hardware configuration of the DUT. 6. The method of claim 1 , wherein a peak power of the reference waveform is increased while performing the iterative direct digital predistortion. 7. A predistortion method for a non-linear device-under-test, DUT, comprising: providing a reference input waveform to the DUT; deriving a predistorted waveform for the DUT based on the reference input waveform using an iterative direct digital predistortion technique; analyzing a relationship between the reference input waveform and the derived predistorted waveform using a mathematical model, wherein the mathematical model comprises a Hammerstein model, a Wiener model, or a Volterra series model; deriving a predistortion algorithm based on said analysis; and applying said predistortion algorithm in a signal generator. 8. The method of claim 7 , wherein the predistortion algorithm compensates non-linear distortions as well as memory effects of the DUT. 9. The method of claim 7 , wherein the signal generator is configured to perform a real-time predistortion of an input signal for the DUT based on said predistortion algorithm. 10. The method of claim 7 , wherein the mathematical model comprises a memory polynomial model. 11. The method of claim 7 , wherein the step of analyzing the relationship between the reference input waveform and the derived predistorted waveform using the mathematical model comprises calculating parameters of the mathematical model, wherein said parameters depend on a hardware configuration of the DUT. 12. A predistortion system for a non-linear device-under-test, DUT, comprising: a signal source configured to generate a reference input waveform to the DUT; a signal analyzer configured to receive an output waveform of the DUT, a processing unit configured to derive a predistorted waveform based on the reference input waveform and the output waveform using an iterative direct digital predistortion technique; wherein the processing unit is configured to analyze a relationship between the reference input waveform and the derived predistorted waveform using a mathematical model, wherein the mathematical model comprises a Hammerstein model, a Wiener model, or a Volterra series model, wherein the processing unit is configured to derive a predistortion algorithm for the DUT based on said analysis; and a predistortion unit configured to apply said predistortion algorithm to an input signal for the DUT. 13. The system of claim 12 , wherein the predistortion unit is configured to perform a real-time predistortion of the input signal based on said predistortion algorithm. 14. The system of claim 12 , wherein the system further comprises: a signal generator configured to feed the, thus, predistorted input signal to the DUT. 15. The system of claim 12 , wherein the predistortion algorithm compensates non-linear distortions as well as memory effects of the DUT.

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Classifications

  • H04B1/0475Primary

    with means for limiting noise, interference or distortion (H04B1/0483 takes precedence) · CPC title

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What does patent US11496166B1 cover?
The present disclosure relates to a predistortion method and a predistortion system for a non-linear device-under-test, DUT. The predistortion method comprises the steps of: providing a reference input waveform to the DUT; deriving a predistorted waveform for the DUT based on the reference input waveform using an iterative direct digital predistortion technique; analyzing a relationship between…
Who is the assignee on this patent?
Rohde & Schwarz
What technology area does this patent fall under?
Primary CPC classification H04B1/0475. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 08 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).